當電子產品正衝擊整個世界，半導體製造的技術進步，晶片製造發展至低成本、高良率，造成更大的影響。嵌入式動態隨機存取記憶體 (DRAM)製程，從製程中串入一段深構製程來製作深構式DRAM，主要的優勢是以“系統單晶片”的概念將DRAM和邏輯區其整合在同一個晶粒上而以DRAM取代部份的靜態隨機存取記憶體。但是新開發的製程技術，良率尚無法達到預期目標。故障分析顯示“缺陷”，電容節間過於擴口及主動區微孔缺陷，是影響良率最主要的因素。本文針對嵌入式記憶體之溝槽式蝕刻製程的缺陷，利用“缺陷檢驗機台” 和“電子顯微鏡”找出缺陷的種類和來源，根據不同種類缺陷形成的機制，提出蝕刻調整改善方案，利用增加溝槽硬罩蝕刻氣體中的氧流量，來解決擴口缺陷，並加入利用縮短電容深溝製程一的蝕刻秒數的實驗設計來從中找尋最佳化的條件。研究結果發現，當硬罩蝕刻的氧流量從23sccm增加到24sccm已可大幅改善擴口的問題，並且將深溝製程的蝕刻時間從120秒縮短至110秒時，微孔缺陷不受硬罩蝕刻的氧流量增加仍可維持最佳化的晶圓，其晶圓良率獲得提昇。

Due to radical advancements of semiconductor process technology, microelectronic chips are manufactured in lower cost with better yield, this makes the impact of electronic merchandises to the world even more noticeable than it already does. One of the most innovative advancement is to add a deep trench step into a Dynamic Random Accessible Memory (DRAM) manufacturing process; this will provide a tremendous advantage by using the concept of SOC (System on Chip) to integrate DRAM and logic in a same die and replace portion of SRAM with DRAM. However, due to spacing from Node-to-Node and defect of Active-Area Pin Hole, this new manufacturing process can not exceed the expected yield. This dissertation proposed an improvement program to improve defects and Node-to-Node spacing problem for deep trench embedded DRAM manufacturing process. The defect data which was exploited to the cause and categorize the class of the defect were acquired by using SEM and KLA. During the research, it was found that Node-to-Node spacing problem can be solved by increased the amount of etch O2 gases for DTMO. Therefore, an experiment was designed to find out the optimized proportion between etching time for DT1 (The 1st stage of Deep Trench manufacturing) and the amount of etching gases for DTMO. Form the results of experiment, it was discovered that if the amount of etching gases for DTMO were increased from 23sccm to 24sccm, it can greatly improve the issue of Node-to-Node spacing. In addition to that, DT1 etching time can decreased from 120 seconds to 110 seconds and Pin-Hole defects were tremendously improved. In conclusion, a wafer which used the optimized proportion between the amount of etching gases and etching time for DT1 gives a better die yield than one without it.

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