本論文研究應用於24-GHz與60-GHz接收機之CMOS射頻晶片之研製。設計的晶片包含24-GHz及60-GHz CMOS收發開關、24-GHz雙平衡式次諧波降頻混頻器與摺疊式混頻器，晶片製作均使用國家晶片中心(CIC)提供之標準TSMC CMOS 0.18 μm 製程或TSMC CMOS 0.13 μm 製程，且均使用on-wafer方式進行量測。
24-GHz收發開關的量測結果顯示之直流偏壓為1.8 V / 0 mA，消耗功率為0 mW，天線端的返回耗損為17.4 dB、接收端的返回耗損為10.8 dB、由於對稱式架構，發射端的返回耗損等同於接收端的返回耗損為10 .8 dB、插入損失為6.0 dB、發射模式時發射端與接收端之間的隔離度為32.4 dB、接收模式時天線端與發射端之間的隔離度為25.8 dB、input P1dB為21.5 dBm、IIP3為32.6 dBm。60-GHz收發開關的量測結果顯示電路之直流偏壓為1.2 V / 0 mA，消耗功率為0 mW，天線端的返回耗損為14.6 dB、接收端的返回耗損為8.4 dB、由於對稱式架構，發射端的返回耗損等同於接收端的返回耗損為8.4 dB、插入損失為11.2 dB、發射模式時發射端與接收端之間的隔離度為34.4 dB、接收模式時天線端與發射端之間的隔離度為21.5 dB、input P1dB為9.5 dBm。
24-GHz次諧波混頻器量測結果顯示混頻器核心電路之直流偏壓為1.5 V / 2.08 mA，消耗功率為3.12 mW，輸出主動平衡器與緩衝放大器之直流偏壓為1.8 V / 7 mA，消耗功率為12.6 mW。RF端輸入的返回耗損大於8 dB、LO端輸入的返回耗損大於10 dB、IF端輸出的返回耗損大於10 dB、轉換增益為4.01 dB、input P1dB為-12.5 dBm、IIP3為-3.25 dBm、LO-RF隔離度為38 dB，LO-IF隔離度為40 dB、RF-IF隔離度為40.5 dB、2LO-RF隔離度為65.5 dB與2LO-IF隔離度為70 dB。
24-GHz摺疊式混頻器模擬結果顯示混頻器核心電路之直流偏壓為1 V / 12 mA，消耗功率為12 mW，緩衝放大器之直流偏壓為1 V / 10 mA，消耗功率為10 mW。RF端輸入匹配大於10 dB、IF端輸出的返回耗損大於10 dB、轉換增益為-0.5 dB、input P1dB為-6 dBm、LO-RF隔離度為43.8 dB，LO-IF隔離度為45 dB、RF-IF隔離度為41.2 dB。

This thesis presents the design of Millimeter-wave CMOS T/R switches, sub-harmonic and folded mixers. The designed CMOS RFICs are fabricated with TSMC CMOS 0.18 μm 1P6M and TSMC 0.13 μm 1P8M standard process. The design of a 24-GHz CMOS T/R switch combines the shunt inductor resonance and body-floating schemes. The T/R switch exhibits a high isolation and good linearity performance. The design of a 24-GHz sub-harmonic mixer and a 24-GHz folded mixer are also presented.

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