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研究生： 許富盛
Hsu, Fu-Sheng
論文名稱： 雙模取樣具最小切換動態元件匹配之14-bit 200MHz數位類比轉換器
A 14-bit 200MHz DAC with Minimum Current Switching and Dynamic Element Matching for Oversampling and Nyquist Dual-Mode
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系碩士在職專班
Department of Electrical Engineering (on the job class)
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 104
中文關鍵詞： 數位類比轉換器 、最小切換 、動態元件匹配
外文關鍵詞： DAC, minimum switching, dynamic element matching
相關次數： 點閱：99  下載：8 
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    • 動態元件匹配技術(DEM)被使用再提升無雜散動態範圍(SFDR)的性能但是他常因為需要額外的元件狀態切換而導致嚴重的突波問題，最小切換動態元件匹配技術(MSDEM)在本論文中被提出來降低突波問題使得突波能量可以跟溫度計解碼器的數位類比轉換器一樣小，在最小切換動態元件匹配技術實現上會有低頻諧波以及高通雜訊移頻的問題，雜訊移頻的補償技巧被使用以減低上述兩個問題，在補償上使用隨機多重資料權重平均法(RMDWA)並且使用它來做為操做在超取樣模式的主要演算法。
    本論文之十四位元數位類比轉換器使用TSMC 1P6M 0.18um CMOS製程實現並且有效面積只有0.099mm2，計算最小面積的方法在本論文中稍做更新以達到較小有效面積，使用電壓為1.8伏特且耗電只有26.8mW，本論文之實做數位類比轉換器可以透過外控訊號使其操作在Nyquist或超取樣模式。

    Dynamic element matching (DEM) is used to increase higher spurious free dynamic range (SFDR) performance but it had serious glitch issue which caused by extra elements status changing. The Minimum Switching Dynamic Element Matching (MSDEM) is proposed to achieve same glitch energy as thermometer decoder based digital to analog converter. Low frequency tone and high pass noise shaping are other issues in MSDEM implementation. Noise shaping compensation technology is proposed in this thesis to reduce the both effects. Random Multiple Date Weighted Averaging (RMDWA) with low pass noise shaping is used to be the compensating algorithm and it will be the major DEM algorithm at oversampling rate mode.
    A 14-bit current steering DAC with MSDEM is implemented by TSMC 0.18um CMOS process with active area 0.099mm2. The new current cell area calculation equation is updated in this thesis to achieve smaller active area. The supply voltage is 1.8V and power consumption is 26.8mW. This DAC can be operated under oversampling or Nyquist rate system by one selection signal.

    Chapter 1 Introduction 15 1.1 Backgrounds 15 1.2 Motivation 17 1.3 Organization 18 Chapter 2 Fundamental of Digital to Analog Converter 19 2.1 Introduction 19 2.2 Oversampling Technology 19 2.3 DAC Architectures 20 2.3.1 Binary Weighted DAC Architecture 20 2.3.2 Unary (Thermometer Code) DAC Architecture 21 2.3.3 Segmented DAC Architecture 23 2.3.4 Binary Weighted Resistor DAC 24 2.3.5 Reduce Resistor DAC 25 2.3.6 R-2R Ladder DAC 26 2.3.7 Charge Redistribution DAC 27 2.3.8 Current Steering DAC 28 2.4 Non-ideal Converter 29 2.4.1 Timing Errors 30 2.4.2 Glitch 30 2.4.3 Non-Linearity Errors 31 2.4.4 Static Performance 32 2.4.5 Dynamic Performance 34 2.4.6 Spectrum Specification 38 2.5 Error Cancellation Technology 39 2.5.1 Calibration Technology 39 2.5.2 Dynamic Element Matching Technology 40 2.5.3 Return to Zero 41 2.5.4 Layout Issue 42 2.6 Summary 42 Chapter 3 Dynamic Element Matching 43 3.1 Introduction 43 3.2 Conventional DEM 43 3.3 DEM for oversampling 43 3.3.1 Tree Structure DEM 44 3.3.2 Convention Data Weighted Averaging 44 3.3.3 Data Weighted Averaging Like Algorithm 46 3.4 DEM for Nyquist Rate 48 3.4.1 Random Multiple Date Weighted Averaging (RMDWA) 48 3.4.2 Random Thermometer Coding (RTC) 51 3.5 Summary 51 Chapter 4 Dual mode Minimum Switching Dynamic Element Matching Algorithm with Noise Shaping Compensation 53 4.1 Introduction 53 4.2 Minimum Switching Dynamic Element Matching Algorithm 54 4.3 Noise Shaping Compensation of MSDEM 58 4.4 RMDWA Performance in Oversampling 64 4.5 Summary 65 Chapter 5 Implementation of a 14-bit 200MHz Current Steering DAC with MSDEM 67 5.1 Introduction 67 5.2 Matching Requirement versus Current Cell Area 67 5.3 Analog Circuit 70 5.3.1 DAC architecture 71 5.3.2 Current cell 72 5.3.3 Bias Circuit 73 5.3.4 Synchronous Circuit 75 5.3.5 Decouple Capacitor 77 5.3.6 Loading impedance compensation 82 5.3.7 Layout Consideration 83 5.4 Digital Circuit 87 5.4.1 Pseudo Random Number Generator 87 5.4.2 Register 88 5.4.3 Non-overlap clock generator 89 5.4.4 Binary to Thermometer Decoder 89 5.4.5 Start Point Calculator 90 5.4.6 Shifter 92 5.5 Experiment Result 92 5.5.1 Pre-simulation Result 92 5.5.2 Layout 94 5.5.3 Post-Simulation Result 95 5.6 Summary 98 Chapter 6 Measurement 100 6.1 Measurement Setup 100 Chapter 7 Conclusions 102 Bibliography 103

    [1]. A. Van den Bosh, M. Steyaert and W. Sansen,. "An Accurate Statistical Yield Model for CMOS Current Steering D/A Converter,". IEEE 2000 Int. Symposium on Circuit and system (ISCAS), Vols. pp. IV.105-IV.108, May 2000,.
    [2]. S. Wong, J. Ting and S. Hsu,. "Characterization and Modeling of MOS Mismatch in Analog CMOS Technology". Proc. of the IEEE Int. Conference on Microelectronic Test Structure (ICMTS), pp.171-176 March 1995.
    [3]. Takahiro Miki, Yasuyuki Nakamura, Masao Nakaya, Sotoju Asai, Yoichi Akasaka, Andyasutaka Horiba. "An 80-MHz 8-bit CMOS D/A Converter,". IEEE Journal of Solid-State Circuits,VOL. SC-21,NO. 6,DECEM8ER 1986.
    [4]. Da-Huei Lee, Yu-Hong Lin and Tai-Haur Kuo,. “Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and QN Rotated Walk Switching Scheme,”. IEEE Transactions on Circuits and Systems II, Vol. 53, No. 11, pp. 1264-1268, Nov. 2006.
    [5]. A. Van den Bosch, M. Steyart et W. Sansen,. "SFDR-Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converter,". Proc. IEEE 1999 Int. Conf. on Electronics, Circuit and Systems (ICECS), pp. 1193-1196, Sept. 1999.
    [6]. Fiex, Rex T. Baird and Terri S. "Improved ΔΣ DAC Linearity Using Data Weighted Averaging,". proceeding of th 1995 IEEE International Symposium on Circuit and System,. vol. 1, pp. 13-16, May 1995.
    [7]. Richard Scherier, Gabor C. Temes. Understanding Delta-Sigma Data Converters. s.l. : Wiley-Interscience, 2005. ISBN 0-471-46585-2.
    [8]. Yu-Hang Lin, Da-Uuei Lee, Cheng-Chung Yang and Tai-Haur Kuo,. “High-speed DACs with Random Multiple Data-Weighted Averaging Algorithm”. ISCAS 2003.
    [9]. Da-Huei Lee, Yu-Hong Lin and Tai-Haur Kuo,. "Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and Rotated Walk Switching Scheme". Circuits and Systems II: Express Briefs, Vol. 53 no. 11, 1264-1268, 2006.
    [10]. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers,. “Matching properties of MOS transistors,”. IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1439, Oct. 1989.
    [11]. Da-Huei Lee, Tai-Haur Kuo, and Kow-Liang Wen,. “Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method”,. IEEE Tranaction on Circuits and System—II: Express Briefs, VOL. 56, NO. 2, FEBRUARY 2009.
    [12]. Seo, Dongwon. “A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter”,. IEEE Journal of Solid-State Circuits, VOL. 42, NO. 3, MARCH 2007.
    [13]. Mikhail Popovich, Andrey V. Mezhiba, Eby G. Friedman. Power Distribution Networks With On-Chip Decoupling Capacitors. s.l. : Springer, 2007. ISBN 978-0-387-71600-8.
    [14]. Van Der Plas, G.A.M., et al. "A 14-bit intrinsic accuracy Q2 random walk CMOS DAC". IEEE Journal of Solid-State Circuits, Vol. 34 , no. 12 Dec. 1999.
    [15]. David A. Johns, Ken Martin. Analog Integrated Circuit Design. s.l. : John Wiley & Sons, inc., 1997. ISBN 0-471-1448-7.
    [16]. Tao Chen, Georges G. E. Gielen,. “A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration”. IEEE Journal of Solid-State Circuits, VOL. 42, NO. 11, NOVEMBER 2007.
    [17]. Qiuting Huang1, Pier Andrea Francese, Chiara Martelli, Jannik Nielsen,. “A 200MS/s 14b 97mW DAC in 0.18μm CMOS”. ISSCC 2004 / SESSION 20 / Digital-to-Analog Converters / 20.3.
    [18]. John Hyde, Todd Humes, Chris Diorio, Mike Thomas, and Miguel Figueroa. “A 300-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS”. IEEE Journal of Solid-State Circuits, VOL. 38, NO. 5, MAY 2003.
    [19]. Yonghua Cong, and Randall L. Geiger,. “A 1.5-V 14-Bit 100-MS/s Self-Calibrated DAC”,. IEEE Journal of Solid-State Circuits, VOL. 38, NO. 12, DECEMBER 2003.
    [20]. Hsin-Hung Chen, Jaesik Lee, Joe Weiner, Young-Kai Chen, and Jiunn-Tsair Chen. “A 14-b 150 MS/s CMOS DAC with Digital Background Calibration”,. 2006 Symposium on VLSI Circuits Digest of Technical Papers.
    [21]. Kok Lim Chan, Jianyu Zhu, and Ian Galton,. “Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs”,. IEEE Journal of Solid-State Circuits, VOL. 43, NO. 9, SEPTEMBER 2008.
    [22]. Mercer, Douglas A. “Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-m CMOS”. IEEE Journal of Solid-State Circuits, VOL. 42, NO. 8, AUGUST 2007.
    [23]. O.Nys and R. Henderson. “An analysis of dynamic element matching techniques in sigma-delta modulation,”. in Proc. ISCAS’96, Atlanta, GA, May 12-15, 1996, pp. 231-234.

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