| 研究生: |
謝武聰 Hsieh, Wu-Tsung |
|---|---|
| 論文名稱: |
U-Net類神經網路模型於電子元件模擬中預測二維物理量 U-Net Neural Network Model Predicting Two-Dimensional Physical Quantities for Electronic Device Simulations |
| 指導教授: |
高國興
Kao, Kuo-Hsing |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering |
| 論文出版年: | 2022 |
| 畢業學年度: | 110 |
| 語文別: | 英文 |
| 論文頁數: | 73 |
| 中文關鍵詞: | 機械學習 、卷積神經網路 、U-Net 、雙閘極金屬氧化物半導體場笑電晶體 、TCAD |
| 外文關鍵詞: | Machine Learning, Convolutional Neural Network, U-Net, Double Gate Metal-Oxide-Semiconductor Field effect transistor (DG-MOSFET), TCAD |
| 相關次數: | 點閱:127 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
由於在資訊科技上應用的良好潛力,機械學習在近年來非常受歡迎。得益於半導體科技的進步,硬體設備的能力越來越好,不論是運算能力,或是資料的蒐集,都比以前更強。完善訓練後的神經網路搭配足夠的資料,能迅速並精確的得出結果,使得它能在各種領域上都能有傑出的發揮。
以自我一致性求解基礎物理方程式的元件數值模擬在減少技術開發與時間的成本上非常有幫助。但不可避免的,元件微縮導致更加微妙的量子效應,以及其餘新的元件物理和參數,這促使了數值問題的產生,並要求有高昂的計算能力。
此研究中我們選擇特定條件下進行數值模擬的一個二維元件,再將結果匯出,使用其中的一部分作為資料集訓練神經網路模型。當神經網路模型被訓練完畢後,便能更快速地計算出元件內部的物理量,並節省傳統的元件模擬所需的時間。
我們也嘗試使用不同的資料集並研究模擬結果的準確度。一個是使用小的資料集訓練神經網路模型,去減少整體的元件模擬時間。另一個則是使用含有不同結構的元件的資料集訓練神經網路模型,並確認模型在面對各種設計的整體表現。
Machine learning is very popular in recent years because of its great potential in the information technology applications. Thanks to the advancement of semiconductor technology, the capabilities of hardware become better. Not only computing power, but also data collection capabilities are stronger than before. With sufficient amount of data, well-trained neural network can predict fast and accurately which promises that it can perform well in many regimes.
Device numerical simulation solving fundamental physics equation self-consistently can be very helpful to reduce technology development cost and time cost. However, it seems unavoidable that MOSFET scaling leads to more subtle quantum effects, other new device physics and parameters that need to be considered to design advanced devices with new materials. This may cause numerical problems and result in expensive computational power.
We choose a two-dimensional device under specific conditions in the numerical simulations and extract the results that are used to be the dataset to train the neural network model. After neural network model is well-trained, it can calculate the physical quantities inside the device more quickly and save the time of traditional device simulations.
We also try using other datasets to study the accuracy of the simulation outcome. One is a smaller amount of dataset to train the neural network model when reducing the total time of device simulations. Another is the dataset which including different structure of devices is used to train the neural network model and check the overall performance on which the model faces the various designs.
[1] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, 19 April 1965.
[2] S. B. Samavedam et al., "Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020.
[3] S.M. Sze, Kwok K. Ng, Physics of Semiconductor Devices.
[4] P. Ongsulee, "Artificial intelligence, machine learning and deep learning," in 2017 15th International Conference on ICT and Knowledge Engineering (ICT KE), 2017.
[5] J.P. Colinge, "Multi-gate SOI MOSFETs," Microelectronic Engineering, vol. 84, no. 9-10, pp. 2071-2076, 2007.
[6] Qiang Chen and Agrawal, B. and Meindl, J.D., "A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 1086-1090, June 2002.
[7] E. a. M. J. Qiang Chen and Harrell, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003.
[8] Frank and Laux and Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?," in 1992 International Technical Digest on Electron Devices Meeting, 1992.
[9] Wong, H.-S.P. and Frank, D.J. and Solomon, P.M. an, "Nanoscale CMOS," Proceedings of the IEEE, vol. 87, no. 4, pp. 537-570, April 1999.
[10] Synopsys, Sentaurus™ Device User Guide Version Q-2019.12, December 2019.
[11] X. He et al., "Impact of aggressive fin width scaling on FinFET device characteristics," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017.
[12] A. V. Thathachary, L. Liu and S. Datta, "Impact of fin width scaling on carrier transport in III-V FinFETs," in 71st Device Research Conference, 2013.
[13] Synopsys, Sentaurus™ Visual User Guide Version Q-2019.12, December 2019.
[14] X. Glorot, A. Bordes, and Y. Bengio, "Deep sparse rectifier neural networks," Journal of Machine Learning Research-Proceedings Track, vol. 15, pp. 315-323, 2011.
[15] LeCun, Y., Bengio, Y. & Hinton, G., "Deep learning," Nature, vol. 521, p. 436–444, 28 May 2015.
[16] J. Long, E. Shelhamer and T. Darrell, "Fully convolutional networks for semantic segmentation," in 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2015.
[17] T. Falk et al., "U-Net: deep learning for cell counting, detection, and morphometry," Nature Methods, vol. 16, p. 67–70, December 2018.
[18] P. F. a. T. B. O. Ronneberger, "U-Net: Convolutional Networks for Biomedical Image Segmentation," in Medical Image Computing and Computer-Assisted Intervention, 2015.
[19] Wong, H.-S.P. and Frank, D.J. and Solomon, P.M., "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," in International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998.
[20] Yuan Taur, "An analytical solution to a double-gate MOSFET with undoped body," IEEE Electron Device Letters, vol. 21, no. 5, pp. 245-247, May 2000.
校內:2027-07-01公開