簡易檢索 / 詳目顯示

回結果列表
研究生： 林勇志
Lin, Yeong-Jyh
論文名稱： 植晶機之取晶過程分析
Pick-up Process Analysis of Die Bonder
指導教授： 黃聖杰
Hwang, Sheng-Jye
學位類別： 博士
Doctor
系所名稱： 工學院 - 機械工程學系
Department of Mechanical Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 121
中文關鍵詞： 田口方法 、植晶機 、薄晶 、砷化鎵 、取晶 、電腦模擬
外文關鍵詞： Die bonder, Taguchi method, Computer simulation, Pick-up process, GaAs, Thin die
相關次數： 點閱：107  下載：13 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 　　為製造出輕、薄、短、小並具備多功能的電子產品以滿足消費者，薄晶片之封裝設計已成為必然的趨勢。砷化鎵半導體材料相對於一般以矽為基底之材料來說具有較佳之電子飄移、輸出功率及低雜訊之特性，使其具有不同於矽基材料之特殊應用範疇。因應高頻與無線通訊之發展需要，砷化鎵材料之需求與發展快速，透過技術面克服其天生脆若的特性。這些趨勢正考驗著封裝技術，當然也包括植晶過程（將晶粒由膠帶上取起並將晶粒放置於封裝載具上）。

    　　本論文首先分析一般植晶機之取晶過程接著透過靜態及動態電腦模擬針對此一取晶過程做更深入之探討，為驗證模擬之結果亦利用機台進行了一些實驗。對砷化鎵晶片來說，最重要的是頂出過程對晶片之破壞程度，因此利用田口方法針對製程參數進行分析，發現頂出速度、植晶力量、頂取高度為最重要的三個因子。分析動態模擬之結果，可發現晶片在頂取瞬間之衝擊力量；頂取時頂針對膠帶之破壞穿透現象可透過模擬結果清楚的觀察到。另外本論文中利用軟體所提供之特殊“黏-斷碰撞”分析技巧將頂取時膠帶緩緩剝離晶片底部之現象模擬出來，使模擬結果更真實。

    　　本文主要針對植晶機之頂取過程提出分析模擬的方法，透過此方法將製程參數最佳化並提升生產量率。除此之外，亦可透過修正調整本分析之模型、邊界條件來針對不同機構之頂取方式進行模擬，甚而發展出新型之頂取方式及機構。

    　Thin die is the mainstream for the packages to achieve the goal of manufacturing compact and light products with higher functionality for customers. Gallium arsenide (GaAs) has some unique properties that make it ideal for using in applications that silicon is ill-suited for, such as the characteristics of high mobility, high output power, and low noise. With the demand for the high frequency and wireless applications, requirement and development in GaAs circuits have dramatically progressed to overcome the inherently fragile behavior. These trends challenge many related package process, including the die bonder: a machine to pickup the die from tape and then place it onto a package carrier.

    　In this study, the process to picking up a die for general type of die bonder was comprehensively investigated and then simulated with both static and dynamic computer simulations. Some experiments were also employed to verify the simulation results. The main theme of this thesis is the die cracking due to the ejecting needle, and then the parameter effects were analyzed by means of Taguchi Method. The ejecting speed of needle, bond force of the collet and the ejecting height were found as the significant factor to the die crack. Impact effect of needle and penetration of tape were both observed and discovered from dynamic analysis. Detaching phenomena was also considered and simulated through tie-break contact, supported by LS-Dyna, to make the simulation more factual.

    　A methodology was demonstrated here to study the pickup process for a die bonder. Via this procedure, not only the parameters of the process could be optimized but also the yield was promoted. Besides, this method could be easily modified for simulating other type of die bonders with different mechanisms; even a new procedure could be derived for the next generational die bonder.

    中文摘要 I ABSTRACT II 致謝 IV ACKNOWLEDGEMENTS VII TABLE OF CONTENTS X LIST OF FIGURES XIII LIST OF TABLES XVI CHAPTER 1 INTRODUCTION 1 1.1 IC PACKAGE 2 1.1.1 Package Classification and Types 2 1.1.2 Packaging Process 4 1.2 THIN DIE TRENDS 9 1.2.1 3D Stacked Package 10 1.2.2 Wafer Thinning 11 1.3 DIE BONDING PROCESS 13 1.4 RELATED WORK AND LITERATURE REVIEW 16 1.5 THESIS OVERVIEW 18 CHAPTER 2 ANALYSIS METHODOLOGIES AND RELATED TOPICS 19 2.1 PICK-UP MECHANISM OF A DIE BONDER 20 2.1.1 Mechanical Modules 20 2.1.2 Pick-up Mechanism 23 2.2 COMPUTER SIMULATION 24 2.2.1 Static Analysis 25 2.2.2 Dynamic Analysis 29 2.3 TAGUCHI METHOD 33 2.3.1 Orthogonal Array Experiments 33 2.3.2 The Analysis of Means (ANOM) 34 2.4 GALLIUM ARSENIDE MATERIAL 37 2.5 FRACTURE MECHANISM OF GAAS MATERIAL 39 2.6 TAPES AND THE ADHESIVE STRENGTH 41 2.6.1 UV Tape 41 2.6.2 Peeling of the Tape 42 2.6.3 Adhesive Strength 43 CHAPTER 3 STATIC ANALYSIS 46 3.1 CRITICAL STAGES FOR STATIC ANALYSIS 47 3.2 PROCESS PARAMETERS AND ORTHOGONAL ARRAY 49 3.3 DYNAMIC EFFECT TRANSFORM 51 3.4 FINITE ELEMENT SIMULATION 53 3.4.1 Simplification 53 3.4.2 Finite Element Modeling 54 3.4.3 Material Property 55 3.4.4 Boundary Condition 56 3.5 ANALYSIS RESULT 60 3.5.1 Stage I 60 3.5.2 Stage II 62 3.5.3 Result of Taguchi Method 63 3.5.4 Die Crack Issue 66 CHAPTER 4 DYNAMIC ANALYSIS 67 4.1 WHY DYNAMIC ANALYSIS 68 4.2 ADHESIVE STRENGTH EVALUATION 69 4.3 FINITE ELEMENT SIMULATION 71 4.3.1 Simplification 71 4.3.2 Finite Element Modeling 73 4.4.3 Material Property 75 4.3.4 Boundary Condition 77 4.4 ANALYSIS RESULTS 80 4.4.1 Deformation and Stress Distribution 80 4.4.2 Dynamic Effect 83 4.4.3 Detach Behavior of Tape 84 CHAPTER 5 RESULTS AND DISCUSSION 86 5.1 MESH SENSITIVITY 87 5.1.1 Static Analysis 87 5.1.2 Dynamic Analysis 89 5.2 INTERACTION INVESTIGATION 92 5.2.1 Analysis Method 92 5.2.2 Interaction of factors in Stage I Analysis 92 5.2.3 Interaction of factors in Stage II Analysis 98 5.2.4 Summary of the Interaction 102 5.3 PENETRATION OF TAPE 104 5.3.1 Rupture Criterion 104 5.3.2 Analysis Results and Discussion 105 5.3.3 Summary of the Tape Rupture 108 5.4 EXPERIMENTS 109 CHAPTER 6 CONCLUSIONS AND FUTURE DIRECTION 111 6.1 CONCLUSIONS 112 6.2 FUTURE DIRECTION 115 REFERENCES 116 BIOGRAPHY 119 LIST OF PUBLICATIONS 120 Journal Papers 120 Conference Papers 120

    [1] R. J. Hannemann, A. D. Kraus, and M. Pecht, Semiconductor Packaging: A Multidisciplinary Approach, New York: John Wiley & Sons, 1994.
    [2] M. G. Pecht, L.T. Nguyen, and E.B. Hakim, Plastic-Encapsulated Microelectronics, New York: John Wiley & Sons, 1995, pp. 1-21.
    [3] FUJITSU LIMITED, electronic devices, “To Top/Package Lineup/Package Index,” April 2004 <http://edevice.fujitsu.com/fj/DATASHEET/readmee/contents.pdf>.
    [4] L. C. Hwang, “Study of Warpage Due to P-V-T-C Relation of EMC in IC Packaging,” P.H.D. thesis, Dep. of Mechanical Engineering, National Cheng Kung University, Tainan, Taiwan, 2004.
    [5] K. Y. Chen, Robert L. D. Zenner, Michael Arneson, and David Mountain, “Ultra-Thin Electronic Device Package,” IEEE TRANSACTIONS ON ADVANCED PACKAGING, Vol. 23, No. 1, pp. 22-26, February 2000.
    [6] E. Gaulhofer and H. Oyrer, “Wafer Thinning and Strength Enhancement to Meet Emerging Packaging Requirements,” IEMT Europe 2000 Symposium (IEEE/CPMT), Munich, Germany, 2000.
    [7] Marcos Karnezos, “3-D Packaging: Where All Technologies Come Together,” 2004 IEEE/SEMI Int'l Electronics Manufacturing Technology Symposium, Vol.29, San Jose, United States, 2004, pp. 64-67.
    [8] T. Cordner, and B. Marks, “GaAs Wafer Breakage: Causes and Cures, Growth and Process,” Proc. 15th Annu. Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, San Jose, 1993, pp. 317-320.
    [9] R. P. Vidano, D. W. Paananen, T. H. Miers, J. M. Krause-Singh, K. R. Agricola, and R. L. Hauser, “Mechanical Stress Reliability Factors for Packaging GaAs MMIC and LSIC Components,” IEEE Transaction on Components, Hybrid, and Manufacturing Technology, vol. 10, pp. 612-617, December 1987.
    [10] P. Neathway and F. Cantua, “Pick-and-place Machine Analysis,” Surface Mount Technology, vol. 12, no. 10, pp. 54-58, October 1998.
    [11] M. Nishiguchi, A. Miki, N. Goto, M. Fujihira, and H. Nishizawa, “High Mechanical Reliability of Back-Ground GaAs LSI Chips with Low Thermal Resistance,” IEEE Transaction on Components, Hybrid, and Manufacturing Technology, vol. 14, pp. 848-854, December 1991.
    [12] Gallant Precision Machining Company Limited, IC Packaging Front End Equipment, Die bonder - K2200, < http://www.gpmcorp.com.tw/KB-2200.htm >.
    [13] Introduction semiconductor die products, International Electrotechnical Commission Standard 62258 Part 3, 2003.
    [14] ANSYS User’s Manual Volume IV Theory 1st Revision, ANSYS INC., SAS IP September 30, 1994.
    [15] Hallquist, John O., LS-DYNA Theoretical Manual, Livermore Software Technology Corporation (1998).
    [16] W. Y. Fowlkes, and C. M. Creveling, Engineering Methods for Robust Product Design: Using Taguchi Methods in Technology and Product Development, Addison-Wesley Publishing Company, 1995.
    [17] E. A. Fattakhov, T. D. Lisovskaya, and A. V. Roshchina, JZV. Akad. Navk SSSR, Inerg. Mater., vol. 16, pp. 1669-1671, 1980.
    [18] Y. Morishima, S.-I. Ishiwata, H. Maruyama, H. Miyagi, Y. Kanou and T. Aoi, “Development of Anti-static UV-tapes for Semiconductor Processing,” FURUKAWA REVIEW, No. 22, September, 2002. <http://www.furukawa.co.jp>
    [19] Standard Test Method for Pressure-Sensitive Adhesive-Coated Tapes used for Electrical and Electronic Applications, ASTM Standard D 1000, 1999.
    [20] C.-C. Chou, “A Study of the Diecracking due to Die Injection,” M.S. thesis, Dept. Mechanical Engineering, Chung Yuan Christian University, Chung-Li, Taiwan, 1998.
    [21] W. Brostow, and R. D. Corneliussen, Failure of Plastics, New York: Hanser, 1986, pp. 25-29.
    [22] W. D. Callister, Jr., Materials Science and Engineering: An Introduction, 3rd Ed., John Wiley & Sons, 1997.
    [23] ANSYS Manual LS-Dyna User’s Guide, ANSYS INC., SAS IP, 2003.

    下載圖示 校內：立即公開
    校外：2005-07-20公開
    QR CODE