本研究以模擬探討全包覆閘極奈米片場效電晶體 (Gate-All-Around Nanosheet Field-Effect Transistor, GAA NSFET) 之短通道效應(Short-Channel Effects, SCEs) 抑制技術。我們提出兩種結構性改良方案，包含單獨與結合槽式內側間隔層 (Trench Inner Spacer, TIS) 與非對稱閘極 (Asymmetric Gate, AG) 佈局，以增強元件的靜電控制能力。TIS 垂直插入基板，可以有效限制汲極電場向底部基板方向的穿透，並阻擋底部基板寄生通道形成所造成的漏電流；AG 則可降低汲極與底部基板寄生通道間的電容耦合。此外，本研究亦調整基板接地層摻雜 (Ground Plane Doping, GPD) 濃度，以強化底部基板區域的電位障壁。為了進一步評估其低功耗操作潛力，本研究亦針對低供應電壓 (low-VDD) 條件進行元件特性模擬，以分析所提出結構在未來低電壓邏輯應用中的可行性。所有元件層級模擬皆使用 Synopsys Sentaurus TCAD 進行，並進一步透過 TCAD Mixed-Mode CMOS 模擬評估所提出結構在電路層級的效能表現。
模擬結果顯示，本研究提出的結構組合可顯著抑制短通道效應，包括有效降低汲極誘發能障降低 (Drain-Induced Barrier Lowering, DIBL)、改善次臨界擺幅 (Subthreshold Swing, SS)，並大幅降低關態電流 (Ioff)。在 1.5 nm 節點 NSFET 中，DIBL 與 SS 的整體改善幅度最高均超過 25%，而 Ioff更降低達接近兩個數量級；同時在 low-VDD操作下仍能保持良好的靜電控制特性與開關性能。綜合而言，本研究提出之結構設計大幅提升元件可縮放性、降低漏電流，並展現出於低功耗應用中的高度潛力。

This study investigates short-channel effects (SCEs) suppression techniques for gate-all-around nanosheet field-effect transistors (GAA NSFETs) through device simulations. Two structural optimization approaches are proposed, including the individual and combined implementation of a trench inner spacer (TIS) and an asymmetric gate (AG), to enhance electrostatic control. The TIS, vertically extended into the substrate, suppresses drain electric field penetration toward the bottom substrate parasitic channel, thereby reducing leakage current. The AG configuration further alleviates parasitic capacitive coupling between the drain and the bottom substrate region. In addition, ground plane doping (GPD) is optimized to strengthen the potential barrier in the bottom substrate.

Device characteristics under low supply voltage (low-VDD) operation are also examined to evaluate the feasibility of the proposed structures for low-power logic applications. All device-level simulations are performed using Synopsys Sentaurus TCAD, and circuit-level performance is evaluated through TCAD mixed-mode CMOS simulations.

Simulation results show that the proposed structures effectively suppress SCEs, including reduced drain-induced barrier lowering (DIBL), improved subthreshold swing (SS), and significantly lowered off-state current (Ioff). For a 1.5-nm-node NSFET, DIBL and SS improve by more than 25%, while Ioff is reduced by nearly two orders of magnitude. These results indicate that the proposed designs enhance scalability, suppress leakage, and are promising for low-power logic applications.

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