近年來，由於電子產品的不斷進步與革新，對IC的輕薄短小、高頻、高速與高散熱率需求日增，使得覆晶封裝體等可縮小IC面積的封裝產品成為產品主流，故本文將針對直接晶片接合封裝體進行研究，探討封裝體導電層之受力狀況，希望透過分析能了解導電層之脆弱處以確保產品之品質穩定。
本文使用ANSYS12.0有限元素分析軟體對直接晶片接合封裝體進行分析，施予模型從-45℃至125℃的溫度循環負載，其中錫球考慮為彈塑性材料，其他材料視為彈性材料。在分析時採用全域/局部模型分析法，在全域模型中將導電層以等效參數取代，並在局部模型中還原導電層各層，使其達到精準性與收斂性，並觀察導電層受力行為，並發現高溫時Y方向應力極值-231.06Mpa發生於最下層之氧化層底部，低溫時Y方向應力極值-371.448Mpa發生於最上層之銅層，形成可能脫層與剝落之位置，並作為標準形式。
其次，改變溫度循環負載如：改變高溫、低溫、恆溫時間、升降溫率，並與標準形式作比較，觀察導電層應力大小之改變與破懷模式。最後改變導電層結構，增加導電層中銅層之層數，分析與標準形式之差異。將這些因子作比較顯示導電層結構中銅層數影響最大，在4層銅層與8層銅層比較下，銅層層數越多，低溫時導電層各層Y方向應力增加，其中銅層與氧化層分別增加31.7%與23.3%，高溫時應力則是減少，銅層與氧化層分別減少102%與128%。

In recent years, with the continuous progress and innovation of the electronic products progress, the requirements for frivolous short, high frequency, high speed and the high heat emission to the IC chip has increased. As a result, the flip chip and some similar packages which are facilitated to reduce the IC area become the mainstream product in the market. By adopting the Direct Chip Attach Package, this paper aims to investigate the stress condition at the conducting layer of the package so as to figure out the fragile location of the conducting layer and ensure the stability of product quality.

The ANSYS 12.0 finite element analysis is employed as well as the Direct Chip Attach Package is subjected by the thermal cycle of -45℃~125℃. The solder ball is considered as elasticplastic while other components are treated as elastic. The Global/Local Method is adopted for analysis. The material properties of the conducting layer is replaced by equivalent parameters in the global model and the original parameters are restored to each conducting layer in the local model so as to achieve certain accuracy and convergence, and then the stress behaviors of the conducting layer are investigated. It is found that the maximum Y component of stress is -231.06Mpa located at the bottom of oxide layer in high temperature while the maximum Y component of stress is -371.448Mpa located at the top of the copper layer in low temperature. It seems that the two locations are easy to delaminate and crack. The above model is regarded as the standard model.

Secondly, the temperature cycle loading, such as high temperature, low temperature, time of constant temperature and the heat rate, is changed to compare with the standard model in which the stress changing and the failure mode in the conducting layer are observed. Finally, the structure of the conducting layer is changed, such as the increase of the amount of copper layers, to analyze its difference from the standard model. By comparing with those factors, the amount of copper layers is more significant factor which is changed from 4 copper layers to the 8 copper layers for the structure of the conducting layer, it shows that more copper layers in conducting layers, higher Y component of stress happening in each part of conducting layers in low temperature. Y component of stress is 31.7% increasing in copper layers and 23.3% increasing in oxide layers. It also shows the opposite results in high temperature where Y component of stress is 102% decreasing in copper layers and 128% decreasing in oxide layers.

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