由非易失性儲存器（NVM）技術組成的持久儲存器，提供了更細微的存取粒度、高速隨機存取速度以及非易失性等特性，模糊了傳統工作儲存器與永久存儲裝置之間 的界限。但是，持久儲存器仍然需要保持崩潰一致性（Crash Consistency）和容錯性；否則，由於停電或系統崩潰導致的數據不一致將永久存在於非易失性儲存器中。近期的研究計畫使用「放寬資料所需之保存時間（Retention Relaxation）」機制來提高持久儲存系統的性能；不幸的是，他們沒有保持崩潰一致性。在這篇論文中，我們提出了一種嶄新的物件型持久儲存器所使用的儲存系統，稱作「漫遊者（Rover System）」。通過放寬之前研究所沒有被放寬的持久性物件的保存時間，來有效利用NVM特性、提高系統存取之性能。此外，漫遊者使用簡單卻又強大的預測策略來預測物件所需之保存時間。為了保持崩潰一致性，漫遊者引入了持久性等級（Durability Levels）的概念，是個在耐久性和性能之間的折衷。

Persistent memory which is composed of Non-volatile Memory (NVM) technologies, provides characteristics like finer-granularity access, fast random-access speed, and non-volatility, blurs the line between traditional working memory and persistent storage. However, persistent memory still needs to maintain crash consistency and fault tolerance; otherwise, the data inconsistency owing to power outage or system crashes will resides in NVM permanently. Recent proposals use a retention relaxation mechanism to improve persistent memory system’s performance; unfortunately, they did not maintain crash consistency. In this paper, we propose Rover System, a novel transaction object-based persistent memory storage system with retention relaxation mechanism, to leverage NVM characteristics and improve system I/O performance via relax the retention requirement on persistent object which previous research did not relax on. In addition, Rover System use a simple yet powerful prediction policy to predict object’s retention requirement. To maintain crash consistency, Rover System introduce the concept of durability levels, a trade-off between durability and performance.

[1] B. C.Lee, E.Ipek, O.Mutlu, andD.Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” Isca’09, 2009.
[2] M. K.Qureshi, V.Srinivasan, andJ. a.Rivers, “Scalable High Performance Main Memory System Using Phase-Change Memory Technology,” ACM SIGARCH Comput. Archit. News, vol. 37, no. 3, p. 24, 2009.
[3] P.Zhou, B.Zhao, J.Yang, andY.Zhang, “A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology,” Proc. 36th Annu. Int. Symp. Comput. Archit. - ISCA ’09, p. 14, 2009.
[4] M.Qureshi, J.Karidis, andM.Franceschini, “Enhancing Lifetime and Security of PCMBased Main Memory with Start-Gap Wear Leveling,” Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchitecture, p. 14, 2009.
[5] E.Kultursay, M.Kandemir, A.Sivasubramaniam, andO.Mutlu, “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” ISPASS 2013 - IEEE Int. Symp. Perform. Anal. Syst. Softw., pp. 256–267, 2013.
[6] X.Fong, Y.Kim, R.Venkatesan, S. H.Choday, A.Raghunathan, andK.Roy, “SpinTransfer Torque Memories: Devices, Circuits, and Systems,” Proc. IEEE, vol. 104, no. 7, pp. 1449–1488, 2016.
[7] H.Akinaga andH.Shima, “Resistive Random Access Memory (ReRAM) Based on Metal Oxides,” Proc. IEEE, vol. 98, no. 12, pp. 2237–2251, Dec.2010.
[8] C.Xu et al., “Overcoming the Challenges of Crossbar Resistive Memory Architectures,” IEEE 21st Int. Symp. High Perform. Comput. Archit., pp. 476–488, 2015.
[9] D.Kau, “Dielectric thin film on electrodes for resistance change memory devices,” U.S. Patent No 9,287,498, 2016.
[10] D. G.Andersen, J.Franklin, M.Kaminsky, A.Phanishayee, L.Tan, andV.Vasudevan, “FAWN: A Fast Array of Wimpy Nodes,” Sosp ’09, pp. 1–14, 2009.
[11] S.Pelley, T. F.Wenisch, B. T.Gold, andB.Bridge, “Storage Management in the NVRAM Era,” Proc. VLDB Endow., vol. 7, no. 2, pp. 121–132, 2013.
[12] J.Huang, K.Schwan, andM. K.Qureshi, “NVRAM-aware Logging in Transaction Systems,” Proc. VLDB Endow., vol. 8, no. 4, pp. 389–400, 2014.
[13] J.-Y.Jung andS.Cho, “Memorage: Emerging Persistent RAM based Malleable Main Memory and Storage Architecture,” Ics ’13, p. 115, 2013.
[14] S. R.Dulloor et al., “System Software for Persistent Memory,” EuroSys’14, pp. 1–15, 2014.
[15] S.Kannan, A.Gavrilovska, andK.Schwan, “Reducing the Cost of Persistence for Nonvolatile Heaps in End User Devices,” Proc. - Int. Symp. High-Performance Comput. Archit., pp. 512–523, 2014.
[16] D. R.Chakrabarti, H.-J.Boehm, andK.Bhandari, “Atlas: Leveraging Locks for Non-volatile Memory Consistency,” Proc. 2014 ACM Int. Conf. Object Oriented Program. Syst. Lang. Appl., pp. 433–452, 2014.
[17] T.Ching-Hsiang Hsu, H.Brügner, I.Roy, K.Keeton, andP.Eugster, “NVthreads: Practical Persistence for Multi-threaded Applications,” EuroSys’17, pp. 1–2, 2017.
[18] M.Wu andW.Zwaenepoel, “eNVy: A Non-Volatile, Main Memory Storage System,” Proc. IEEE 4th Work. Workstn. Oper. Syst. WWOS-III, pp. 25–28, 1993.
[19] J.Condit et al., “Better I/O Through Byte-Addressable, Persistent Memory,” Proc. ACM SIGOPS 22nd Symp. Oper. Syst. Princ. (SOSP ’09), pp. 133–146, 2009.
[20] X.Wu andA. L. N.Reddy, “SCMFS: A File System for Storage Class Memory,” Proc. 2011 Int. Conf. High Perform. Comput. Networking, Storage Anal., p. 39:1-39:11, 2011.
[21] H.Volos, S.Nalli, S.Panneerselvam, V.Varadarajan, P.Saxena, andM. M.Swift, “Aerie: Flexible File-System Interfaces to Storage-Class Memory,” Proc. 9th Eur. Conf. Comput. Syst. EuroSys 2014, 2014.
[22] J.Xu andS.Swanson, “NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories,” 14th USENIX Conf. File Storage Technol. (FAST 16), pp. 323–338, 2016.
[23] A. M.Caulfield, A.De, J.Coburn, T. I.Mollov, R. K.Gupta, andS.Swanson, “Moneta: A High-performance Storage Array Architecture for Next-generation, Non-volatile Memories,” in Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 2010, pp. 385–395.
[24] A. M.Caulfield, T. I.Mollov, L. A.Eisner, A.De, J.Coburn, andS.Swanson, “Providing Safe, User Space Access to Fast, Solid State Disks,” ACM SIGARCH Comput. Archit. News, vol. 40, no. 1, p. 387, 2012.
[25] A.Akel, A. M.Caulfield, T. I.Mollov, R. K.Gupta, andS.Swanson, “Onyx: A Protoype Phase Change Memory Storage Array,” HotStorage’11 Proc. 3rd USENIX Conf. Hot Top. storage file Syst., p. 2, 2011.
[26] A. M.Caulfield et al., “Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing,” 2010 ACM/IEEE Int. Conf. High Perform. Comput. Networking, Storage Anal. SC 2010, no. November, 2010.
[27] H.Volos, A. J.Tack, andM. M.Swift, “Mnemosyne: Lightweight Persistent Memory,” ACM SIGPLAN Not., vol. 47, no. 4, pp. 91–103, 2012.
[28] J.Coburn et al., “NV-Heaps: Making Persistent Objects Fast and Safe with Next-Generation, Non-Volatile Memories,” Asplos, 2011.
[29] A.Chatzistergiou, M.Cintra, andS. D.Viglas, “REWIND: Recovery Write-Ahead System for In-Memory Non-Volatile Data-Structures,” Vldb ’15, pp. 497–508, 2015.
[30] I.Moraru, D. G.Andersen, M.Kaminsky, N.Tolia, P.Ranganathan, andN.Binkert, “Consistent, Durable, and Safe Memory Management for Byte-addressable Non Volatile Main Memory,” Proc. First ACM SIGOPS Conf. Timely Results Oper. Syst. - TRIOS ’13, pp. 1–17, 2013.
[31] “Direct Access for files.” [Online]. Available: https://www.kernel.org/doc/Documentation/filesystems/dax.txt.
[32] “The future of the page cache.” [Online]. Available: https://lwn.net/Articles/712467/.
[33] T.Wang andR.Johnson, “Scalable Logging through Emerging Non-Volatile Memory,” in Proceedings of the VLDB Endowment, 2014, vol. 7, no. 10, pp. 865–876.
[34] J.Coburn, T.Bunker, M.Schwarz, R.Gupta, andS.Swanson, “From ARIES to MARS: Transaction Support for Next-Generation, Solid-State Drives,” ACM Symp. Oper. Syst. Princ. (SOSP ’13), pp. 197–212, 2013.
[35] J.Arulraj, A.Pavlo, andS. R.Dulloor, “Let’s Talk About Storage & Recovery Methods for Non-Volatile Memory Database Systems,” Proc. 2015 ACM SIGMOD Int. Conf. Manag. Data, no. 1, pp. 707–722, 2015.
[36] Q.Hu, J.Ren, A.Badam, andT.Moscibroda, “Log-Structured Non-Volatile Main Memory,” ATC ’17, May2017.
[37] “Deprecating the PCOMMIT Instruction.” [Online]. Available: https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction.
[38] E.Lee, S.Yoo, J. E.Jang, andH.Bahn, “Shortcut-JFS: A Write Efficient Journaling File System for Phase Change Memory,” IEEE Symp. Mass Storage Syst. Technol., pp. 1–6, 2012.
[39] S.Venkataraman, N.Tolia, P.Ranganathan, andR. H.Campbell, “Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory,” Proc. 9th USENIX Conf. File Storage Technol. - FAST, pp. 61–75, 2011.
[40] J.Yang, Q.Wei, C.Chen, C.Wang, K. L.Yong, andS.Clara, “NV-Tree : Reducing Consistency Cost for NVM-based Single Level Systems,” USENIX Conf. File Storage Technol., 2015.
[41] S.Chen andQ.Jin, “Persistent B+-Trees in Non-Volatile Main Memory,” Proc. VLDB Endow., vol. 8, no. 7, pp. 786–797, 2015.
[42] R.Fang, H. I.Hsiao, B.He, C.Mohan, andY.Wang, “High Performance Database Logging using Storage Class Memory,” Proc. - Int. Conf. Data Eng., pp. 1221–1231, 2011.
[43] E.Lee, H.Bahn, andS. H.Noh, “Unioning of the Buffer Cache and Journaling Layers with Non-volatile Memory,” in Proceedings of the 11th USENIX Conference on File and Storage Technologies (FAST 13), 2013.
[44] J.Zhao, S.Li, D. H.Yoon, Y.Xie, andN. P.Jouppi, “Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support,” Proc. 46th Annu. IEEE/ACM Int. Symp. Microarchitecture - MICRO-46, pp. 421–432, 2013.
[45] J.Izraelevitz, T.Kelly, andA.Kolli, “Failure-Atomic Persistent Memory Updates via JUSTDO Logging,” Asplos, pp. 427–442, 2016.
[46] “Persistent Memory Development Kit.” [Online]. Available: http://pmem.io/pmdk/.
[47] J.Arulraj, M.Perron, andA.Pavlo, “Write-Behind Logging,” Proc. VLDB Endow., vol. 10, no. 4, pp. 337–348, 2016.
[48] H.Wan, Y.Lu, Y.Xu, andJ.Shu, “Empirical Study of Redo and Undo Logging in Persistent Memory,” 2016 5th Non-Volatile Mem. Syst. Appl. Symp. NVMSA 2016, 2016.
[49] C.Chen et al., “Fine-grained Metadata Journaling on NVM,” Msst, 2016.
[50] L.Sun, Y.Lu, andJ.Shu, “DP2: Reducing Transaction Overhead with Differential and Dual Persistency in Persistent Memory,” Proc. 12th ACM Int. Conf. Comput. Front. -CF ’15, pp. 1–8, 2015.
[51] Y.Lu, J.Shu, andL.Sun, “Blurred Persistence in Transactional Persistent Memory,” IEEE Symp. Mass Storage Syst. Technol., 2015.
[52] Y.Lu, J.Shu, L.Sun, andO.Mutlu, “Loose-Ordering Consistency for Persistent Memory,” 2014 32nd IEEE Int. Conf. Comput. Des. ICCD 2014, pp. 216–223, 2014.
[53] A.Joshi, V.Nagarajan, S.Viglas, andM.Cintra, “ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging,” Hpca ’17, 2017.
[54] M.Liu, M.Zhang, K.Chen, andX.Qian, “DUDETM: Building Durable Transactions with Decoupling for Persistent Memory,” Asplos ’17, 2017.
[55] D.Narayanan andO.Hodson, “Whole-System Persistence,” ACM SIGARCH Comput. Archit. News, vol. 40, p. 401, 2012.
[56] J.Ren, J.Zhao, S.Khan, J.Choi, Y.Wu, andO.Mutlu, “ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems,” Proc. 48th Int. Symp. Microarchitecture - MICRO-48, pp. 672–685, 2015.
[57] A.Jog et al., “Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs,” Proc. Des. Autom. Conf., pp. 243–252, 2012.
[58] C. W.Smullen IV, V.Mohan, A.Nigam, S.Gurumurthi, andM. R.Stan, “Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches,” Proc. - Int. Symp. High-Performance Comput. Archit., pp. 50–61, 2011.
[59] X.Dong andY.Xie, “AdaMS: Adaptive MLC/SLC Phase-Change Memory Design for File Storage,” in 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, pp. 31–36.
[60] R.-S.Liu, D.-Y.Shen, C.-L.Yang, S.-C.Yu, andC.-Y. M.Wang, “NVM Duet: Unified Working Memory and Persistent Store Architecture,” Proc. 19th Int. Conf. Archit. Support Program. Lang. Oper. Syst. - ASPLOS ’14, pp. 455–470, 2014.
[61] M.Zhang, L.Zhang, L.Jiang, Z.Liu, andF. T.Chong, “Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor,” Hpca ’17, pp. 385–396, 2017.
[62] A.Sampson, J.Nelson, K.Strauss, andL.Ceze, “Approximate Storage in Solid-State Memories,” Proc. 46th Annu. IEEE/ACM Int. Symp. Microarchitecture, vol. 32, no. 3, pp. 25–36, 2013.
[63] R.Liu, C.Yang, andW.Wu, “Optimizing NAND Flash-Based SSDs via Retention Relaxation,” Fast, vol. 11, no. 10, p. 80, 2012.
[64] Y.Luo, Y.Cai, S.Ghose, J.Choi, andO.Mutlu, “WARM: Improving NAND Flash Memory Lifetime with Write-hotness Aware Retention Management,” 2015.
[65] Y. S.Lee, S. H.Kim, J. S.Kim, J.Lee, C.Park, andS.Maeng, “OSSD: A Case for Object-based Solid State Drives,” IEEE Symp. Mass Storage Syst. Technol., 2013.
[66] Y.Kang, Y.Jingpei, andE. L.Miller, “Object-based SCM: An Efficient Interface for Storage Class Memories,” IEEE Symp. Mass Storage Syst. Technol., 2011.
[67] Y.Pan, G.Dong, Q.Wu, andT.Zhang, “Quasi-Nonvolatile SSD: Trading Flash Memory Nonvolatility to Improve Storage System Performance for Enterprise Applications,” in IEEE International Symposium on High-Performance Comp Architecture, 2012, pp. 1–10.
[68] F.Chen, T.Luo, andX.Zhang, “CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives,” Engineering, pp. 77–90, 2011.
[69] S.Peter et al., “Arrakis : The Operating System Is the Control Plane,” ACM Trans. Comput. Sytem, 2016.
[70] M.Balakrishnan, A.Kadav, V.Prabhakaran, andD.Malkhi, “Differential RAID: Rethinking RAID for SSD Reliability,” ACM Trans. Storage, vol. 6, no. 2, pp. 1–22, Jul.2010.
[71] “UEFI Specifications.” [Online]. Available: http://uefi.org/specifications.
[72] “LIBNVDIMM: Non-Volatile Devices.” [Online]. https://www.kernel.org/doc/Documentation/nvdimm/nvdimm.txt.