為了維持邏輯互補型金氧半場效電晶體的尺寸持續微縮及提高元件性能，高介電常數介電層與金屬閘電極技術已成為製程技術最重要的基礎研究之一。近年來，很多新穎的高介電材料被提出來取代二氧化矽，其中最佳選擇之一為二氧化鉿。然而二氧化鉿本身缺陷也很多，它會使P型金氧半場效電晶體產生嚴重的缺陷捕捉效應，進而導致電性與可靠度的問題。另外在奈米級電晶體內中會有過量的低頻雜訊(包含1/f雜訊與隨機擾動雜訊)產生，因而限制類比、數位、混訊與射頻等線路功能。
本論文，為了改善上述的問題，首先研究使用離子佈植技術摻入不同的鋁能量與濃度製作P型二氧化鉿高介電金氧半場效電晶體，並探討該元件的低頻雜訊之響應。透過低頻雜訊分析，除可觀測不同的鋁能量與濃度對於元件特性影響外，並能進一步了解元件低頻雜訊的物理機制，擴展未來研究的領域。
對於具有不同的鋁能量與濃度佈植之二氧化鉿P型金氧半場效電晶體中，根據實驗結果顯示使用鋁離子佈植到二氧化鉿，可填補二氧化鉿裡的缺陷進而形成一層薄氧化鋁，使得P型金氧半場效電晶體之驅動電流與等效功函數能夠被有效提升，並且透過1/f雜訊與隨機擾動雜訊分析，發現鋁離子佈植後不僅有效的降低穿隧衰退長度以及庫倫散射，增加能障高度，減少了低頻雜訊並且改善了電晶體的品質，同時缺陷深度也比未摻入鋁的元件更靠近二氧化矽/矽介面。然而，當鋁離子佈植的能量與濃度增加時，雖然二氧化鉿缺陷還是有被填補進而形成一層薄氧化鋁，但高的鋁能量與濃度會使鋁擴散太深(靠近二氧化矽/矽介面)，進而增加了等效氧化層厚度和引起閘極穿隧電流密度，使性能降低與雜訊增加。因此更多的研究必須進行探討來萃取最佳化的鋁離子佈植參數以避免高的鋁能量與濃度擴散到更深的矽基板導致可靠度和性能下降。
最後，我們同樣利用高介電係數材料二氧化鉿透過最佳參數的鋁離子佈植並結合氟來製作P型金氧半場效電晶體，並與未結合氟的P型金氧半場效電晶體來進行比較。在結合氟的P型金氧半場效電晶體中，發現驅動飽和電流高於未結合氟的金氧半場效電晶體，並且進一步透過1/f雜訊與隨機擾動雜訊的分析發現結合氟的P型金氧半場效電晶體雜訊小於未結合氟的P型金氧半場效電晶體，故知氟離子佈植更能有效的降低穿隧衰退長度以及庫倫散射，同時也增加了能障高度。並且這二種元件的缺陷位置分別在緩衝介面層中(二氧化矽)，與高介電係數閘極氧化層中，這使得兩種元件的雜訊行為與產生機制不同，這樣的結果顯現出結合氟的P型金氧半場效電晶體對低頻雜訊特性與元件電性具有本質上的好處。

In past several decades, the enormous development for complementary metal-oxide-semiconductor (CMOS) technology was based on conventional silicon oxide dielectric and poly-Si gate electrode. Due to the downscaling of device dimensions in CMOS technology, high-k (HK) materials and metal gate (MG) electrodes have become an important foundation of CMOS technology processes. In this thesis, HfO2-based gate dielectrics are one of the best choices for replacing SiO2. But the intrinsic defects of HfO2 gate dielectrics have caused serious trapping effects in p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) and resulted in some reliability and electrically issues. On the other hand, excessive low-frequency noise, which includes 1/f noise and random telegraph noise (RTN) in nanoscale transistors, leads to a limitation in the functionality for analog, digital, mixed-signal, and RF circuits. In order to improve these problems, we have investigated the behaviors of low-frequency drain current noise using the different energies and doses of Al ion implantation (I/I) into HK layer of pMOSFETs devices. By utilizing the 1/f noise analysis, we can understand the response of traps properties for the different energies and doses of Al I/I pMOSFETs devices of 28-nm technique process.
For Al I/I in the pMOSFETs, this discrepancy should be attributed to the fact that the Al implantation could fill the defects and form a thin Al2O3 layer, so that the drive current and effective work function of the pMOSFETs can be effectively improved. Through the 1/f noise and RTN analysis, as a result, the tunneling barrier height φB became larger for holes and the tunneling attenuation length () penetrating into the dielectric became shorter. However, the energies and doses of Al I/I increased, the Al implantation also could fill the defects and form a thin Al2O3 layer. Higher energies and concentrations of Al have deeply diffused near SiO2/Si interface accompanied with increasing equivalent oxide thickness and caused gate tunneling current density performance degradation due to non-optimized Al implantation. Therefore more studies need to carry out to optimize the Al profiles and to minimize the induced worsening of gate leakage by the deep diffusion of Al into the Si substrate.
Finally, we have investigated of low-frequency noise of 28-nm technology process of Al I/I in HK/MG p-MOSFETs with fluorine (F) incorporation. The Drain current in devices with F incorporation is significantly higher than the without F incorporation device counterpart. The oxide trap density (Nt) with F incorporation devices are significantly lower than the without F incorporation device respectively, as a result of λ decreasing. In addition, by using the RTN, the trap depth (XT) of F incorporation devices are located closer to the IL/Si interface maybe result from for F passivating oxygen vacancies and defect sites.

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