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研究生: 陳俊宇
Chen, Chun-Yu
論文名稱: 應用釓含氮覆蓋層、矽鍺通道及氧氣後續沉積退火增進High-k/Metal Gate CMOSFET特性和可靠度之研究
Improvement of High-k/Metal Gate CMOSFET Performances and Reliability with Gadolinium Cap Incorporated Nitrogen,SiGe Channel and Oxygen Post Deposition Annealing
指導教授: 方炎坤
Fang, Yean-Kuen
共同指導教授: 葉文冠
Yeh, Wen-Kuan
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 112
中文關鍵詞: 釓覆蓋層矽鍺通道後續沉積退火
外文關鍵詞: Gd cap layer, SiGe channel, post deposition annealing
相關次數: 點閱:100下載:1
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  • 吾人在以鉿(Hf)為基底的高介電常數氧化層上加入釓(Gd)覆蓋層以降低碳化鉭(TaC)金屬閘極的功函數以及臨界電壓。然而釓原子卻會透過該高介電常數氧化層擴散到基版,造成我們所不希望看到的缺陷。因此我們利用後續氮化處理來減少缺陷的產生以及降低閘極漏電流。但後續氮化處理中電漿也會促成氮原子擴散到釓覆蓋層並在閘極上方堆積及阻擋釓原子,進而產生本體缺陷造成元件正偏壓溫度不穩定性(PBTI)的劣化。我們觀察在釓覆蓋層中氮原子的擴散行為同時透過二次離子質譜儀、低頻雜訊分析和電荷幫浦量測系統檢查該高介電常數薄膜元件中缺陷的位置。
    此外,藉由控制矽鍺通道和矽覆蓋層的厚度來抑制鍺原子的擴散同時將載子侷限在應變矽鍺層,並且避免在表面產生嚴重的寄生通道。藉由最佳化的通道厚度比例設計,我們可得到比高介電常數薄膜搭配金屬閘極結構的矽通道元件更高性能與可靠度的P型矽鍺通道金氧半場效電晶體。除此之外,我們還提出在沉積鉿氧化層(HfO2)後,以通氧氣退火的方式來提升元件的可靠度。實驗結果顯示,以通氧氣做後續沉積退火的方式不會退化元件的驅動電流和等效氧化層厚度。並且明顯的改善包含正偏壓溫度不穩定性、負偏壓溫度不穩定性和與時間相依的介電質崩潰測試等可靠度。

    Gadolinium (Gd) cap layer on the Hf-based high-k dielectric is proposed to reduce effective work function (EWF) and threshold voltage (VTH) of TaC metal gate. However, Gd could diffuse through Hf-based layer into substrate to cause unwanted damages, thus, needing a post NH3 nitridation to suppress these unwanted damages and decrease gate leakage current. Besides, even a NH3 nitridation could improve devices’ performances; however, the nitrogen atoms incorporated in the gate stack via the NH3 plasma treatment could also diffuse into the Gd-cap layer, thus blocking the Gd ions at the top of the Hf-based high-k/metal-gate, which then generate bulk charges to degrade the device’s positive bias temperature instability (PBTI) significantly. We identify the diffusion of nitrogen in the Gd cap layer, as well as the location of trap defects in the Hf-based high-k/metal-gate with secondary ion mass spectrometry (SIMS), flicker noise, and charge pumping measurements.
    Furthermore, we report the optimism channel stack thickness ratio by controlling strained SiGe and Si cap layer thickness to overcome Ge diffusion and confine carriers in strain SiGe layer without formation of a significant parasitic channel at the interface. By optimizing the channel thickness ratio, we achieved higher performance and better reliability Hf-based high-k/metal gate SiGe pMOSFET compared to gate stack on Si channels. Moreover, a post deposition annealing (PDA) including oxygen ion after high-k dielectric deposition was used to improve reliability of the Hf-based high-k/metal gate device. Experiment results showed that the oxygen PDA didn’t degrade the drive current and effective oxide thickness of the Hf-based gate devices. In addition, reliability issues such as PBTI, NBTI and time dependent dielectric breakdown (TDDB) were also improved by the oxygen PDA significantly.

    Contents Abstract (Chinese) i Abstract (English) iii Acknowledgement (Chinese) v Contents vi Figure Captions ix Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 Chapter 2 MOSFET Technology and Device Characterization Inspection 6 2.1 MOSFET Technology 6 2.1.1 Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) 6 2.1.2 High-k/Metal Gate Structure 9 2.1.3 SiGe Channel Technology 14 2.2 Device Characterization Inspection 18 2.2.1 Measurement System 18 2.2.2 ID-VD Measurement 19 2.2.3 ID-VG Measurement 19 2.2.4 C-V Measurement and Hysteresis Inspection 21 2.2.5 Split C-V Measurement and CVC Program Extraction 22 2.2.6 Charge Pumping Technology 23 2.2.7 Low Frequency Noise Analysis 24 2.2.8 Hot Carrier Injection (HCI) Inspection 26 2.2.9 Negative Bias Temperature Instability (NBTI) Inspection 27 Chapter 3 Performance Improvement and Reliability Inspection for Gadolinium Cap Layer and Nitrogen Incorporated Hf-Based High-k/Metal-Gate nMOSFETs 41 3.1 Introduction 41 3.2 Experiments 42 3.3 Results and Discussions 43 3.4 Conclusion 47 Chapter 4 High-k/Metal Gate pMOSFET Performance and Reliability Improvement with Optimism Si cap/SiGe Channel Structure 61 4.1 Introduction 61 4.2 Experiments 62 4.3 Results and Discussions 62 4.4 Conclusion 67 Chapter 5 Improvement of TDDB Reliability and Characteristics of HfO2 High-k/Metal Gate MOSFET Device with Oxygen Post Deposition Annealing 77 5.1 Introduction 77 5.2 Experiments 78 5.3 Results and Discussions 79 5.4 Conclusion 82 Chapter 6 Conclusion and Future Work 91 6.1 Conclusion 91 6.2 Future Work 93 6.2.1 Tunneling Field Effect Transistor (TFET) 94 6.2.2 FinFET 95 References 97

    [2.1] Ben G. Streetman and Sanjay Kumar Banerjee, "Solid state electronic devices", sixth edition.
    [2.2] Mark T. Bohr, Robert S. Chau, Tahir Ghani and Kaizad Mistry, "The high-k solution", IEEE Spectrum, 2007.
    [2.3] S. Inumiya, K. Sekine, S. Niwa, A. Kaneko, M. Sato, T. Watanabe, H. Fukui, Y. Kamata, M. Koyama, A. Nishiyama, M. Takayanagi, K. Eguchi, and Y. Tsunashima, "Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65-nm mode low power CMOS applications", Symp. VLSI Tech. Dig., pp. 17-18, 2003.
    [2.4] G. Lucovsky, B. Rayner, Yu Zhang and J. Whitten, "Experimental determination of band offset energies between Zr silicate alloy dielectrics and crystalline Si substrates by XAS, XPS and AES and ab initio theory: a new approach to the compositional dependence of direct tunneling currents", Electron Devices Meeting, 2002. IEDM '02. Digest. International, pp. 617- 620, 2002.
    [2.5] R. M. Wallace and G. Wilk, "High-k gate dielectric materials", MRS Bulletin, vol. 27, pp. 192-197, 2002.
    [2.6] V. Misra, G. Lucovsky, and G. Parsons, "Issues in High-Gate Stack Interfaces", MRS Bulletin, vol. 27, pp. 212-216, 2002.
    [2.7] C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi level pinning at the poly-Si/metal oxide interface", Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 9-10, 2003.
    [2.8] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-k insulator: The role of remote phonon scattering", J. Appl. Phys., vol. 90, pp. 4587-4608, 2001.
    [2.9] S. Datta, G. Dewey, M. Doczy, B. S. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick, and R. Chau, "High mobility Si–SiGe strained channel MOS transistors with HfO2/TiN gate stack", IEDM Tech. Dig., pp. 653-656, 2003.
    [2.10] Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T. J. King, and C. Hu, "Dual metal gate technology for deep-submicron CMOS transistors", Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 72-73, 2000.
    [2.11] Y. H. Xie, "SiGe field effect transistors", Materials Science and Engineering, vol. 25, pp. 89-121, 1999.
    [2.12] M. P. Temple, D. J. Paul, Y. T. Tang, and A. M. Waite, "Compressively-strained, buried-channel Si0.7Ge0.3 p-MOSFETs fabricated on SiGe virtual substrates using a 0.25um CMOS process", IEEE Trans. Electron Devices, vol. x, 2004.
    [2.13] J. M. Hinckley, V. Sankaran, and J. Singh, "Charged carrier transport in Si1-xGex pseudomorphic alloys matched to Si strain-related transport improvements", Appl. Phys. Lett., vol. 55, pp. 2008-2010, 1989.
    [2.14] J. M. Hinckley, and J. Singh, "Hole transport theory in pseudomorphic Si1-xGex alloys grown on Si (001) substrates", Phys. Rev. B, vol. 41, pp. 2912-2926, 1990.
    [2.15] R. People, J. C. Bean, D. V. Lang, A. M. Sergent, and H. L. Stormer, K. W. Wecht, R. T. Lynch, and K. Baldwin, "Modulation doping in GexSi1-x/Si strained layer heterostructures", Appl. Phys. Lett., vol. 45, pp. 1231-1233, 1984.
    [2.16] M. M. Rieger and P. Vogl, "Electronic-band parameters in strained Si1-xGex alloys on Si1-y Gey substrates", Phys. Rev. B, vol. 48, pp. 14276-14287, 1993.
    [2.17] T. E. Whall and E. H. C. Parker, "SiGe-Heterostructures for CMOS technology", Thin Solid Films, vol. 367, pp. 250-259, 2000.
    [2.18] P. W. Li, E. S. Yang, Y. F. Yandg, J. O. Chu, and B. S. Meyerson, "SiGe pMOSFET’s with gate oxide fabricated by microwave electron cyclotron resonance plasma processing", IEEE Electron Device Lett., vol. 15, pp. 402-405, 1994.
    [2.19] I. S. Goh, J. F. Zhang, S. Hall, W. Eccleston, and K. Werner, "Electrical properties of plasma-grown oxide on MBE-grown SiGe", Semicond. Sci. Technol., vol. 10, pp. 818-828, 1995.
    [2.20] P. W. Li, H. K. Liou, E. S. Yang, S. S. Lyer, T. P. Smith III, and Z. Lu, "Formation of stoichiometric SiGe oxide by electron cyclotron resonance plasma", Appl. Phys. Lett., vol. 60, pp. 3265-3267, 1992.
    [2.21] Deepak K. Nayak, Ph. D. Dissertation, University of California Los Angeles, 1992.
    [2.22] F. K. LeGoues, R. Rosenberg, T. Nguyen, J. Himpsel, and B. S. Meyerson, "Oxidation studied of SiGe", J. Appl. Phys., vol. 65, pp. 1724-1728, 1989.
    [2.23] S. L. Wu, and S. J. Chang, "Si field-effect transistor with doping dipole in buffer layer", Appl. Phys. Lett., vol. 75, pp. 2848-2850, 1999.
    [2.24] K. O. Jeppson, and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices", J. Appl. Phys., vol. 48, pp. 2004-2014, 1997.
    [2.25] S. Mahapatra, M. A. Alam, P. B. Kumar, T. R. Dalei, D. Varghese, and D. Saha, "Negative bias temperature instability in CMOS devices", Microelectron. Eng., vol. 80, pp. 114-121, 2005.

    [3.1] T. Hori, Gate Dielectrics and MOS ULSIs. Berlin, Germany: Springer-Verlag, 1997.
    [3.2] M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi, and A. Nishiyama, "Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics", IEDM Tech. Dig., pp. 849-852, 2002.
    [3.3] C. H. Choi, S. J. Rhee, T. S. Jeon, N. Lu, J. H. Sim, R. Clark, M. Niwa, and D. L. Kwong, "Thermally stable CVD HfOxNy advanced gate dielectrics with poly-Si gate electrode", IEDM Tech. Dig., pp. 857-860, 2002.
    [3.4] N. Umezawa, K. Shiraishi, K. Torii, M. Boero, T. Chikyow, H. Watanabe, K. Yamabe, T. Ohno, K. Yamada, and Y. Nara, "Role of nitrogen atoms in reduction of electron charge traps in Hf-based high-k dielectrics", IEEE Electron Device Lett., vol. 28, pp. 363-365, 2007.
    [3.5] C. Choi, C.-S. Kang, C. Y. Kang, S. J. Rhee, M. S. Akbar, S. A. Krishnan, M. Zhang, and J. C. Lee, "Positive bias temperature instability effects of Hf-based nMOSFETs with various nitrogen and silicon profiles", IEEE Electron Device Lett., vol. 26, pp. 32-34, 2005.
    [3.6] M. S. Akbar, H.-J. Cho, R. Choi, C. S. Kang, C. Y. Kang, C. H. Choi, S. J. Rhee, Y. H. Kim, and J. C. Lee, "Optimized NH3 annealing Process for high-quality HfSiON gate oxide", IEEE Electron Device Lett., vol. 25, pp. 465-467, 2004.
    [3.7] C. C. Hobbs, L. R. C. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, D. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, H.-H. Tseng, S. G.. H. Anderson, B. E. White, and P. J. Tobin, "Fermi-level pinning at the polysilicon/metal-oxide interface-Part II", IEEE Trans. Electron Devices, vol. 51, pp. 978-984, 2004.
    [3.8] V. Narayanan, V. Paruchuri, N. Bojarczuk, B. Linder, B. Doris, Y. Kim, S. Zafar, J. Stathis, S. Brown, J. Arnold, M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J.-P. Locquet, D. Lacey, Y. Wang, P. Batson, P. Ronsheim, R. Jammy, and M. Chudzik, "Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond", Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 178-179, 2006.
    [3.9] H. Alshareef, H. Harris, H. Wen, C. Park, C. Huffman, K. Choi, H. Luan, P. Majhi, B. Lee, R. Jammy, D. Lichtenwalner, J. Jur, and A. Kingon, "Thermally stable N-metal gate MOSFETs using La-Incorporated HfSiO dielectric", Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 7-8, 2006.
    [3.10] S. J. Rhee, H.-S. Kim, C. Y. Kang, C. H. Choi, M. S. Akbar, M. Zhang, T. Lee, I. Ok, F. Zhu, S. A. Krishnan, and J. C. Lee, "Structural optimization and electrical characteristics of ultra-thin gadolinium (Gd2O3) incorporated HfO2 n-MOSFETs", Proc. 63rd DRC, vol. 1, pp. 219-220, 2005.
    [3.11] H.-S. Jung, S. Han, H. Lim, Y.-S. Kim, M. Kim, M. Yu, C.-K. Lee, M. Lee, Y.-S. You, Y. Chung, S. Kim, H. Baik, J.-H. Lee, N.-I. Lee, and H.-K. Kang, "Dual high-k gate dielectric technology using selective AlOx etch (SAE) process with nitrogen and fluorine incorporation", Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 162-163, 2006.
    [3.12] M. Aoulaiche, M. Houssa, W. Deweerd, L. Trojman, T. Conard, J.W. Maes, S. De Gendt, G.. Groeseneken, H. E. Maes, and M. M. Heyns, "Nitrogen incorporation in HfSiO(N)/TaN gate stacks: Impact on performances and NBTI", IEEE Electron Device Lett., vol. 28, pp. 613-615, 2007.
    [3.13] M. Aoulaiche, M. Houssa, T. Conard, S. De Gendt, G. Groeseneken, H. E. Maes, and M. M. Heyns, "Postdeposition-anneal effect on negative bias temperature instability in HfSiON gate stacks", IEEE Trans. Device Mater. Rel., vol. 7, pp. 146-151, 2007.
    [3.14] B. J. O’Sullivan, R. Mitsuhashi, H. Okawa, N. Sengoku, T. Schram, G. Groeseneken, S. Biesemans, T. Nakababyashi, A. Ikeda and M. Niwa, "Defect profiling and the role of nitrogen in lanthanum oxide-capped high-k dielectrics for nMOS applications", Proc. Int. Conf. Solid State Devices Mater., pp. 680-681, 2008.
    [3.15] G. Thareja, H. C. Wen, R. Harris, P. Majhi, B. H. Lee, and J. C. Lee, "NMOS compatible work function of tan metal gate with gadolinium oxide buffer layer on Hf-based dielectrics", IEEE Electron Device Lett., vol. 27, pp. 802-804, 2006.
    [3.16] H. D. Xiong, D. Heh, M. Gurfinkel, Q. Li, Y. Shapira, C. Richter, G. Bersuker, R. Choi, and J. S. Suehle, "Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise and charge pumping measurements", Microelectron. Eng., vol. 84, pp. 2230-2234, 2007.
    [3.17] M. Sato, N. Umezawa, N. Mise, S. Kamiyama, M. Kadoshima, T. Morooka, T. Adachi, T. Chikyow, K. Yamabe, K. Shiraishi, S. Miyazaki, A. Uedono, K. Yamada, T. Aoyama, T. Eimori, Y. Nara, and Y. Ohji, "Physical understanding of the reliability improvement of dual high-k CMOSFETs with the fifth element incorporation into HfSiON gate dielectrics", Proc. Symp. VLSI Technol., pp. 66-67, 2008.
    [3.18] J. Buckley, M. Bocquet, G. Molas, M. Gely, P. Brianceau, N. Rochat, E. Martinez, F. Martin, H. Grampeix, J. P. Colonna, A. Toffoli, V. Vidal, C. Leroux, G. Ghibaudo, G. Pananakakis, C. Bongiorno, D. Corso, S. Lombardo, B. DeSalvo, and S. Deleonibus, "In-depth Investigation of Hf-based high-k dielectrics as storage layer of charge-trap NVMs", IEDM Tech. Dig., pp. 1-4, 2006.
    [3.19] M. Sato, K. Yamabe, K. Shiraishi, S. Miyazaki, K. Yamada, C. Tamura, R. Hasunuma, S. Inumiya, A. AoShanware, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, J. McPherson, and L. Colombo, "Characterization and comparison of the charge trapping in HfSiON and HfO2 gate dielectrics", IEDM Tech. Dig., pp. 38.6.1-38.6.4, 2003.
    [3.20] J. P. Kim, Y.-S. Kim, H. J. Lim, J. H. Lee, S. J. Doh, H.-S. Jung, S.-K. Han, M.-J. Kim, J.-H. Lee, N.-I. Lee, H.-K. Kang, K.-P. Suh, and Y.-S. Chung, "HCI and BTI characteristics of ALD HfSiO(N) gate dielectrics as the compositions and the post treatment conditions", IEDM Tech. Dig., pp. 125-128, 2004.

    [4.1] J. Huang, P. D. Kirsch, J. Oh, S. H. Lee, J. Price, P. Majhi, H. R. Harris, D. C. Gilmer, D. Q. Kelly, P. Sivasubramani, G. Bersuker, D. Heh, C. Young, C. S. Park, Y. N. Tan, N. Goel, C. Park, P. Y. Hung, P. Lysaght, K. J. Choi, B. J. Cho, H.-H. Tseng, B. H. Lee and R. Jammy, "Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT", VLSI Technology, 2008 Symposium on, pp. 82-83, 2008.
    [4.2] G. D.Wilk, R. M.Wallace, and J. M. Anthony, "High-k gate dielectrics: current status and materials properties considerations", J. Appl. Phys., vol. 89, pp. 5243–5275, 2001.
    [4.3] H. R. Harris, P. Kalra, P. Majhi, M. Hussain, D. Kelly, J. Oh, D. Heh, C. Smith, J. Barnett, P. D. Kirsch, G. Gebara, J. Jur, D. Lichtenwalner, A. Lubow, T. P. Ma, G. Sung, S. Thompson, B. H. Lee, H.-H. Tseng, and R. Jammyet, "Band-engineered low PMOS VT with high-k/metal gates featured in a dual channel CMOS integration scheme", Proc. Symp. VLSI Technol., pp. 154–155, 2007.
    [4.4] J. M. Hinckley, V. Sankaran, and J. Singh, "Charged carrier transport in Si1-xGex pseudomorphic alloys matched to Si strain-related transport improvements", Appl. phys. Lett., vol. 55, pp. 2008-2010, 1989.
    [4.5] J. M. Hinckley and J. Singh, "Hole transport theory in pseudomorphic Si1-xGex alloys grown on Si (001) substrates", Phys. Rev. B, vol. 41, pp. 2912-2926, 1990.
    [4.6] S. L. Wu, "SiGe δ-channel field-effect transistors on SIMOX substrates", Semicond. Sci. Technol., vol. 20, pp. 559-562, 2005.
    [4.7] Z. Shi, D. Onsongo, and S. K. Banerjee, "Mobility and performance enhancement in compressively strained SiGe channel pMOSFETs", Appl. Surf. Sci., vol. 224, pp. 248-253, 2004.
    [4.8] G. K. Dalapati, S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, Y. L. Tsang, R. Agaiby, A. G. O’Neill, P. Dobrosz, and S. J. Bull, "Impact of strained- Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs", IEEE Trans. Electron Devices, vol. 53, pp. 1142–1152, 2006.
    [4.9] F. K. LeGoues, R. Rosenberg, T. Nguyen, J. Himpsel, and B. S. Meyerson, "Oxidation studied of SiGe", J. Appl. Phys., vol. 65, pp. 1724-1728, 1989.
    [4.10] S. Suthram, P. Majhi, G. Sun, P. Kalra, H. R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. J. Cho, M. M. Hussain, C. Smith, S. Banerjee, W. Tsai, S. E. Thompson, H. H. Tseng, and R. Jammy, "High performance pMOSFETs using Si/Si1−xGex/Si quantum wells with high-k/metal gate stacks and additive uniaxial strain for 22 nm technology node", IEDM Tech. Dig., pp. 727–730, 2007.
    [4.11] Jungwoo Oh; P. Majhi, R. Jammy, R. Joe, A. Dip, T. Sugawara, Y. Akasaka, T. Kaitsuka, T. Arikado and M. Tomoyasu, "Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si Cap and high-k metal gate stacks", VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on, pp. 22-23, 2009.
    [4.12] Zhonghai Shi, David Onsongo, Sanjay K. Banerjee, "Mobility and performance enhancement in compressively strained SiGe channel PMOSFETs", Applied Surface Science, vol. 224, pp. 248-253, 2004.
    [4.13] S. Tam, P. K. Ko, and C. Hu, "Lucky-electron model of channel hot-electron injection in MOSFETs", IEEE Trans. Electron Devices, vol. 31, pp. 1116-1125, 1984.
    [4.14] S. L. Wu, and S. J. Chang, "Si field-effect transistor with doping dipole in buffer layer", Appl. Phys. Lett., vol. 75, pp. 2848-2850, 1999.
    [4.15] H.D. Xiong, D. Heh, M. Gurfinkel, Q.Li, Y. Shapira, C. Richter, G. Bersuker, R. Choi, and J.S. Suehle, "Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise and charge pumping measurements", Microelectronic Engineering, vol. 84, pp. 2230-2234, 2007.

    [5.1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics : current status and materials properties considerations", J. Appl. Phys., vol. 89, pp. 5243–5275, 2001.
    [5.2] B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeitzoff, R. W. Murto, L. Larson and C. Ramiller, "Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)", Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 859-862, 2004.
    [5.3] J. Robertson, "High dielectric constant gate oxides for metal oxide Si transistors", Rep. Prog. Phys., vol. 69, pp. 327–396, 2006.
    [5.4] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the VT instability in SiO2/HfO2 gate dielectrics", Proc. 41st Annual IEEE Intl. Reliability Physics Symp., pp. 41-45, 2003.
    [5.5] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, "Threshold Voltage Instabilities in High-k Gate Dielectric Stacks", IEEE Transactions on Device and Materials Reliability, vol. 5, pp. 45-64, 2005.
    [5.6] Hokyung Park, Rino Choi, Seung Chul Song, Man Chang, C. D. Young, G. Bersuker, Byoung Hun Lee, J. C. Lee and H. Hwang, "Decoupling of cold carrier effects in hot carrier reliability of HfO2 gated nMOSFETs", Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International, pp. 200-203, 2006.
    [5.7] M. Sato, N. Umezawa, J. Shimokawa, H. Arimura, S. Sugino, A. Tachibana, M. Nakamura, N. Mise, S. Kamiyama, T. Morooka, T. Eimori, K. Shiraishi, K. Yamabe, H. Watanabe, K. Yamada, T. Aoyama, T. Nabatame, Y. Nara, Y. Ohji, "Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects", Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1-4, 2008.
    [5.8] K. Torii, H. Kitajima, T. Arikado, K. Shiraishi, S. Miyazaki, K. Yamabe, M. Boero, T. Chikyow, K. Yamada, "Physical model of BTI, TDDB and SILC in HfO2-based high-k gate dielectrics", Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 129-132, 2004.
    [5.9] A. S. Foster, F. Lopez Gejo, A. L. Shluger, and R. M. Nieminen, "Vacancy and interstitial defects in hafnia", Phys. Rev. B, vol. 65, pp. 174117, 2002.
    [5.10] K. Xiong, Y. Du, K. Tse, J. Robertson, "Defect states in the high-dielectric-constant gate oxide HfSiO4", Journal of Applied Physics, vol. 101, pp. 024101, 2007.
    [5.11] G. Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra, and R. Choi, "Progressive Breakdown Characteristics of High-K/Metal Gate Stacks", IRPS, pp. 49-54, 2007.
    [5.12] H. D. Xiong, D. Heh, M. Gurfinkel, Q. Li, Y. Shapira, C. Richter, G. Bersuker, R. Choi, and J. S. Suehle, "Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise and charge pumping measurements", Microelectronic Engineering, vol. 84, pp. 2230-2234, 2007.

    [6.1] M. Lundstrom, "Moore’s law forever?", Science, vol. 299, pp. 210-211, 2003.
    [6.2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K. Cambridge Univ. Press, 1998.
    [6.3] International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: www.itrs.net
    [6.4] S. Banerjee,W. Richardson, J. Coleman, and A. Chatterjee, "A new three terminal tunnel device", IEEE Electron Device Lett., vol. 8, pp. 347–349, 1987.
    [6.5] M. Born, K. K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, "Tunnel FET: A CMOS device for high temperature applications", Proc. 25th Int. Conf. Microelectron., vol. 1/2, pp. 131–134, 2006.
    [6.6] K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering", IEEE Trans. Electron Devices, vol. 52, pp. 909–917, 2005.
    [6.7] O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered hetero junctions", IEEE Electron Device Lett., vol. 29, pp. 1074–1077, 2008.
    [6.8] J. Knoch, S. Mantl, and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one dimensional devices", Solid State Electron., vol. 51, pp. 572–578, 2007.
    [6.9] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) less than 60 mV/dec", IEEE Electron Device Lett., vol. 28, pp. 743–745, 2007.
    [6.10] P.-F. Wang, K. Hilsenbeck, Th. Ninchl, M. Oswald, Ch. Stepper, M. Weis, D. Schmitt-Landsiedel, W. Hansch, "Simulation of the Esaki-tunneling FET", Solid-State Electronics, vol. 47, pp. 1187-1192, 2003.
    [6.11] W. Reddiek, G. Amaratunga, "Silicon surface tunnel transistor", Appl. Phys. Lett., vol. 67, pp. 494-496, 1995.
    [6.12] C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, S. Deleonibus, "Lateral interband tunneling transistor in silicon-on-insulator", Appl. Phys. Lett., vol. 84, pp. 1780-1782, 2004.
    [6.13] D. Pham, L. Larson, and J.–W. Yang, "FINFET Device Junction Formation Challenges", Int. Workshop on Junction Technology, pp. 73-77, 2006.
    [6.14] L. Risch, "Pushing CMOS beyond the roadmap", Proc. of ESSDERC, pp. 63-68, 2005.
    [6.15] E. J. Nowak, T. Ludwig, I. Aller, J. Kedzierski, M. Ieong, B. Rainey, M. Breitwisch, V. Gemhoefer, J. Keinert and D. M. Fried, "Scaling Beyond the 65 nm Node with FinFET-DGCMOS", Int. Conf. on Custom Integrated Circuit, pp. 339-342, 2003.

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