本論文研究利用具有高沉積速率與能提供大量氫自由基特性的電場輔助熱鎢絲化學氣相低溫沉積法(Bias-assisted HWCVD, BAHWCVD)，首次於負(N)型(100)矽基板上使用甲烷、矽甲烷與氫氣成長奈米碳化矽雙層通道薄膜電晶體。吾人利用FTIR、Raman量測原子間的鍵結、XRD量測薄膜結晶、SEM與AFM觀察表面結構與粗糙度、ESCA測量薄膜中矽原子與碳原子之含量。利用電場輔助所沉積者為非晶碳化矽，具有較高電阻率故用來作為上通道層以降低薄膜電晶體的off-current。下通道主要作為電晶體導通時的路徑，故使用具有較高導電度的奈米碳化矽以增加on-current。藉由雙層通道的設計可以同時降低off-current及提升開關電流比。
實驗結果顯示，薄膜中矽原子與碳原子的比例、鎢絲溫度與基板偏壓對於影響薄膜結構有顯著之影響。且使用非晶碳化矽與奈米碳化矽的雙層通道薄膜電晶體具有比單層奈米碳化矽通道薄膜電晶體較低之暗電流(9.2×10-10 A)與較高開關電流比(1.38×104)。又雙層通道薄膜電晶體場效遷移率為1.13 cm2/Vs也優於已發表的多晶碳化矽薄膜電晶體的0.02 cm2/Vs與多晶矽薄膜電晶體的1.05 cm2/Vs。

The nano-crystalline silicon carbide thin film transistors (nc-SiC TFTs) prepared by a bias-assisted hot-wire chemical vapor deposition (HWCVD) system are investigated in details. The nc-SiC thin films were deposited on Si substrates using CH4, SiH4, and H2 gas mixture. We use FTIR, Raman, XRD, AFM, SEM, and ESCA for bond structure measurement, analyzing crystallinity, examination of surface roughness and morphology, and investigation of carbon atomic concentration in the film, respectively.
The nc-SiC TFTs are designed with an higher resistivity amorphous layer deposited by the bias-assisted HWCVD for the top channel layer; while the layer deposited by the system without the DC bias has a high conductivity nano structure as the bottom channel. As a result, the developed double-channel nc-SiC TFT has lower off-current (9.2×10-10 A) and higher on-off current ratio (1.38×104) than its counter part single-channel nc-SiC TFT. Besides, the double-channel TFT possesses a field effect mobility of 1.13 cm2/Vs, which is also higher than that of 0.02 cm2/Vs for a poly-SiC TFT, and 1.05 cm2/Vs for a poly-Si TFT.

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