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研究生: 張鈞博
Chang, Chun-Po
論文名稱: NAND 型快閃記憶體其周邊電路元件之崩潰電壓與可靠度研究
Breakdown Voltage and Reliability Studies of Devices in NAND Flash Memory Periphery Circuitry
指導教授: 陳志方
Chen, Jone-Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 61
中文關鍵詞: 崩潰電壓熱載子可靠度
外文關鍵詞: Breakdown Voltage, HCI Reliability
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  • NAND Flash 元件在目前可攜式產品上有很高的使用率,而在控制NAND Flash元件儲存與讀取皆需要外部的周邊電路來完成。而本論文研究其周邊電路內部的高壓元件,這次所使用的元件為空乏型橫向擴散場效電晶體,由於高壓元件操作於高壓的環境,因此的崩潰電壓與可靠度為重要的指標,此元件在N- 漂移區域有使用BF2 來調變部分摻雜濃度,濃度改變後此元件的崩潰電壓與熱載子可靠度會有所改變,由於探討此製程的參考文獻並不多,所以我們以此做為本論文的研究目標。
    在第一部分有關於崩潰電壓的研究,因為是常開型元件,所以在關閉時須耐高壓,因此在通道關閉的狀況下,我們研究其崩潰機制,我們發現到有兩個機制在主導崩潰電壓,在沒有摻雜BF2的元件以閘極引發汲極漏電流的崩潰機制為主,而當元件摻雜BF2濃度越濃時以反向PN介面崩潰電壓為主,而我們以TCAD模擬與電性量測來進行驗證。
    在第二部分有關於熱載子可靠度的研究,在元件開關的流程,此元件會遇到熱載子退化的狀況,儘管ISUB通常為退化指標,但我們發現元件退化的大小並沒隨著ISUB的電流值增減,經過charge pumping和TCAD的實驗驗證,我們從模擬結果發現雖然發生離子衝擊化的範圍比較小,但是因為位置集中於drain端導致退化增大,最後從實驗結果推論出影響元件退化的載子種類。

    In this thesis, we study the high-voltage device which is depletion-mode lateral diffused metal-oxide-semiconductor (LDMOS). The HV device in the periphery circuit is applied to NAND Flash Cell for Program/Erase operation. In periphery circuit, the high off-state breakdown voltage (off-state VBD) is an important requirement for this device. Therefore, the LDMOS breakdown mechanism with different BF2 implant by varying implant dosage in N- region is investigated. As expected, the off-state breakdown voltage increase with the raise of BF2 concentration. Experimental data and technology computer aided design simulations show that gate-induced-drain-leakage (GIDL) and PN junction breakdown are responsible for the variation of breakdown voltage.
    Moreover, in the circuit operating environment, there might be hot carrier degradation in the device. The damage will happen while device is programming or erasing data. Generally, the ISUB peak will be the index of the HCI degradation. However, in our study, the measurement results contradict pervious study because the distribution of the impact ionization peak would dominant the hot carrier degradation instead of the amount of the ISUB current. The impact ionization which is located near drain side is greater with higher BF2 concentration. In conclusion, the device with higher BF2 implant suffers worse HCI degradation because of more high energy carrier injection.
    According to the results in this study, care should be taken when we implant the BF2 into the drift region, since there is a trade-off between VBD and HCI reliability issue.

    中文摘要 I Abstract III 致謝 V Content VI Figure Captions VIII Table Caption XI Chapter 1 Introduction and motivation 1 1-1 NAND flash and Periphery Circuitry brief introduction 1 1-2 Introduction to high voltage MOS 2 1-3 GIDL breakdown introduction 2 1-4 P-N junction breakdown 4 1-5 Hot carrier introduction 5 References 11 Chapter 2 Device characteristic and measurement setup 13 2-1 Introduction 13 2-2 Device structure discretion 13 2-3 Measurement methodology 14 2-3-1 VBD measurement 14 2-3-2 ID-VG measurement 15 2-3-3 Hot carrier stress meaurement 15 2-3-4 Charge pumping measurement 15 2-4 Summary 17 Reference : 24 Chapter 3 The experiments of off-state breakdown 25 3-1 Introduction 25 3-2 Stress condition setup 26 3-3 Result and Discussion 27 3-4 Summary 29 References 38 Chapter 4 The experiment of HCI degradation 40 4-1 Introduction 40 4-2 Stress condition setup 40 4-3 Summary 45 Reference 58 Chapter 5 Conclusion and Future work 60 5-1 Conclusion 60 5-2 Future work 61

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