隨著鐵電材料的快速發展，其獨特的性質已經被廣泛地應用。近年來，基於氧化鉿的鐵電場效電晶體憑藉其出色的可微縮性和CMOS兼容性而在所有鐵電材料中取得領先地位。鐵電電晶體也因此被應用於類神經網路中以執行「記憶體內計算」，而類神經網路的概念是透過電子元件去模擬生物神經系統，它不僅可以減少在計算單元和記憶單元間移動資料之功耗與時間，而且能以大量且平行化的方式加快計算，所以此方法是自然界中最為迅速且較不耗能的資訊傳輸方式。
本論文提出了對於雙閘極鐵電電晶體的新穎概念。首先，我們在Sentaurus TCAD 2019版本中建立了我們自己的二維鐵電電晶體模型，並透過確認double sweep下的電流電壓圖來驗證是否存在鐵電特性。特別的是，隨著閘極長度的改變，memory window (MW) 的大小也因此而受到影響，所以我們嘗試透過外推法去萃取出鐵電層中確切的電容值，並結合MOS結構中的串聯電容概念以解釋上述所提及之現象。
最後，我們提出了獨立雙閘極鐵電電晶體的結構，當我們在執行類神經型態計算時，有別於目前文獻中鐵電電晶體記憶體陣列以一個電晶體(控制元件)搭配一個記憶體(儲存資料)的架構，我們元件的最大優勢是能夠以後閘極(Back-gate)控制是否寫入且儲存所要的資料，因此只需要一個獨立雙閘極鐵電電晶體就能取代傳統的記憶體單元，並且明顯地減少記憶體陣列所需的面積。所以在接下來的模擬中，我們有計畫地去探索前閘極以及後閘極對於元件運作時的影響，而獲得應用該元件時的操作方式。因此無論是要進行寫入、抹除，亦或是要維持住本身所儲存的資料，我們都可以應用此單一元件實現，也驗證了我們當初開發此元件的設計構想。

Since ferroelectric materials were studied, the unique characteristics have been utilized for many applications, in recent years, hafnium oxide based ferroelectric field effect transistor comes out on top because of the excellent scalability and CMOS compatibility. Accordingly, FeFET is an attractive candidate to implement in-memory computing for the neuromorphic neural network which is using electronic devices to mimic biological nervous system. It not only reduces the time of moving data between the computing unit and the memory unit but also eliminate the energy consumption by computing the information parallelly, so this method is the fastest and the lowest power consumption way to transfer the information in nature.
In this thesis, we investigate double-gate FeFET. In order to simulate this idea, we implement the 2D FeFET model by Sentaurus TCAD 2019 version first. This way, we build our own structure and verify if ferroelectricity is existed or not by checking the ID – VG for double sweep. In particular, the memory window (MW) is affected with channel length increases, so the exact capacitance of the ferroelectric layer could be extracted by means of extrapolation, and utilizing the series capacitors in MOS structure to explain this phenomenon.
Finally, we propose the novel concept of independent double-gate FeFET which can be a promising element for neuromorphic application. In conventional crossbar memory array, there are two elements in a memory cell including one transistor (switching element) and one memory (store the data). On the other hand, independent double-gate has the advantage of being able to switch between program enable mode (data programmed into the cell) and program inhibit mode (data not programmed into the cell) with the application of back-gate bias. Thus it can replace the conventional memory cell and reduce the array area significantly. In the following thesis, we explore the inference of back-gate and front-gate on our device, then obtain the instructions of operating this device. Therefore, the device can be programmed or preserved the value discretionarily and verify our novel concept of the structure

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