本論文大致分為三個部分，分別為應用於毫米波 V-band 60 GHz CMOS 變壓器結合之功率放大器、W-band 94 GHz CMOS 三級低雜訊放大器以及應用於量子電腦低溫被動元件量測驗證進行研究與討論。晶片製作使用製程皆為台灣半導體研究中心 (TSRI) 提供的標準製程，60 GHz 功率放大器使用的是 TSMC TN90GUTM CMOS 製程，而 94-GHz 低雜訊放大器與低溫被動元件量測驗證使用的是 TSMC TN40G CMOS製程，量測方面皆以 on-wafer 進行量測。
V-band 60 GHz 功率放大器使用了電容性交互耦合中和技術，以抵銷電晶體寄生電容，提升增益與穩定度，在輸入、輸出與級間皆使用變壓器方式進行匹配及差動放大器的結合，以達到完整的訊號傳輸。W-band 94 GHz 低雜訊放大器使用了疊接架構，並且串接三級以達到足夠的增益，佈局的實作上直流電源與偏壓走線，以鋪整片金屬層的方法代替傳統的傳輸線，以降低高頻寄生對電路效能的影響。金屬層的寬度與訊號走線的彎折皆經過適當的選擇，並進行完整電磁模擬驗證。最後一部分為應用於量子電腦低溫被動元件量測驗證，將被動元件 test-key 放入低溫環境量測，量測的溫度包含 300 K、77 K 與 4 K，最後使用 de-embedding 方式，萃取出所設計元件的實際參數，並且驗證其與常溫、低溫與模擬之間的差異性。

This thesis is basically divided into three parts, focusing on the study and discussion in the following areas: a 60 GHz V-band CMOS transformer-based power combining power amplifier (PA) and a 94 GHz W-band CMOS 3-stage low-noise amplifier (LNA) for millimeter-wave (MMW) applications, and passive components for quantum computer applications at cryogenic temperatures. The chip process utilized standard processes provided by the Taiwan Semiconductor Research Institute (TSRI). The 60 GHz PA was designed using the TSMC TN90GUTM CMOS process, while the 94 GHz LNA and cryogenic passive components were designed using the TSMC TN40G CMOS process. All measurements were conducted on-wafer.
For V-band applications, the 60 GHz PA employed capacitive coupling neutralization technique to compensate transistor parasitic capacitance CGD, thereby enhancing gain and stability. Transformer were employed for input, output, and inter-stage matching networks, as well as for differential amplifier coupling to achieve complete signal transmission. For W-band applications, the 94 GHz LNA adopted a cascode architecture with three stages to achieve sufficient gain. In terms of layout implementation, DC power lines and bias lines were designed with a layout method by replacing traditional metal lines with large areas of metal layers, aiming to reduce the impact of high-frequency parasitics on circuit performance. The width of metal layers and the bending of signal traces were carefully chosen, with comprehensive EM simulations to verify the design.
The final part focused on the verification measurements of cryogenic passive components for quantum computer applications. The passive component test-keys were placed in cryogenic environment for measurements at 300 K, 77 K, and 4 K. Finally, a de-embedding technique was used to extract the actual parameters of the designed components, validating the performance differences between the measurement results and simulation data at room temperature and cryogenic temperature.

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