隨著程式高效能的需求持續成長，多核心系統架構成為大部分嵌入式系統的發展趨勢，然而隨著核心數量增加，傳統快取的耗電量也急遽提高。在嵌入式系統中，草稿式記憶體相比於傳統的快取記憶體，耗電量低、面積也小，因此草稿式記憶體被廣泛運用在多核心嵌入式系統中。然而，隨著製程越來越小，由靜態隨機存取記憶體組成的草稿式記憶體的靜態能耗越來越高，為了解決此問題，非揮發性記憶體與靜態隨機存取記憶體組成的混合性草稿式記憶體被廣泛使用於晶片裡的記憶體，以利用非揮發性記憶體的低靜態能耗和高密度的優點，但由於非揮發性記憶體的寫入成本遠大於靜態隨機存取記憶體，所以也必須避免寫入非揮發性記憶體次數過多。在多核心系統下，每個核心有各自的本地端混合性草稿式記憶體，核心上運行的應用程式可以存取本地端與遠端的混合性草稿式記憶體，因此，如果能根據程式需求，分配合適的混合性草稿式記憶體資源給程式，便可以減少非揮發性記憶體的寫入，且提高記憶體使用量，降低耗電量。因此，我們提出了一個動態的混合性草稿式記憶體的即時管理策略，在多核心系統下，根據程式執行期的存取行為去動態分配混合性草稿式記憶體資源，此外，當儲存在非揮發性記憶體裡的資料變成寫入密集時，這筆資料將會被搬移到靜態隨機存取記憶體，以減少非揮發性記憶體的大量寫入。我們的方法結合硬體與軟體的實作。
實驗結果顯示，我們的方法和傳統相同面積的靜態隨機存取記憶體組成的草稿式記憶體相比，在四核心系統與八核心系統下分別可以改善平均效能47%和43%，此外，硬體成本約1.08%

As requirements for high performance keeps growing, multi-core systems have become one of most promising designs in embedded systems. With the number of cores increasing, the energy consumed by cache has become extremely high. Therefore, scratchpad memory (SPM), a software-controlled on-chip memory, have been increasingly adopted in multi-core embedded systems as a substitute for caches. Moreover, due to the increasing leakage power of traditional on-chip SRAM, Hybrid SPM consisting of SRAM and non-volatile memory (NVM) is proposed to exploit the benefits of low leakage power and high density of NVM while avoiding the problem of expensive writes of NVM. In a multi-core system with hybrid SPMs, each core has local hybrid SPM and can access its local hybrid SPM and hybrid SPMs of other cores (i.e., remote hybrid SPMs). Therefore, how to allocate these hybrid SPMs to the tasks running in multi-core systems will influence the energy consumption. This paper proposes a demand-aware online hybrid SPM management for multi-core systems (DOSAM). DOSAM considers the demands of each task and runtime access behaviors to allocate the on-chip SRAM and NVM spaces for each task. In addition, the in-NVM data will be migrated to SRAM when they become write-intensive. DOSAM is implemented by the cooperation of hardware and software.
Evaluation results show that DOSAM can reduce the energy delay product (EDP) by up to 63% (47% on average) in 4-core systems and 57% (43% on average) in 8-core systems, compared to SRAM-based SPMs in multi-core architecture. Furthermore, the hardware area overhead is significant (about 1.08%).

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