本論文於異質性多處理器嵌入式系統平台設計與實作一具有疊置功能之動態程式碼載入機制。此異質性多處理器平台由一ARM7通用型處理器搭配一DSP特殊用途處理器所構成，藉由不同特性處理器之結合以發揮各別處理器之特長：ARM7處理器主要掌控系統平台之運作並負責週邊裝置之溝通；DSP處理器著重於數位訊號之處理並扮演週邊裝置之角色。由於DSP端可用之記憶體空間十分有限，侷限應用程式之開發，本論文採取「以時間換取空間」之策略於此異質性多處理器嵌入式系統平台設計並實作程式碼疊置機制以作為克服記憶體空間限制之一解決方案。

本論文所設計之程式碼疊置機制具有使用者不需修改程式碼、不受編譯器之限制、使用者負擔小等特點且建構於異質性多處理器平台。程式碼疊置機制實作部份之組成包含：ARM端動態載入程式之服務、DSP端疊置管理者、前置處理工具等。執行時期之程式碼疊置機制由動態載入程式之服務與疊置管理者所構成，分別負責程式碼之載入處理與動態載入程式服務之需求提出；又因疊置機制載入器之處理時間為系統效能之瓶頸所在，故需使用前置處理工具將應用程式以函式為單位加以分段並分析其相依性，以大幅減少程式載入需求次數並降低動態處理之負擔。

本論文之疊置機制可解決DSP處理器端程式開發受限記憶體之問題。程式碼結構影響一般疊置機制之效果，對於使用本疊置機制之應用程式而言，因分段處理以目的程式檔為對象，原始程式碼可不必修改；在適當之分段方式下，程式之執行效能亦不會有太大之影響。整體而言，本論文設計之程式碼疊置機制可有效減少程式執行時所需要之記憶體空間並降低軟體開發者規劃程式架構之負擔。

This thesis presents the design and implementation of a dynamic code loading mechanism with overlay functionality on an embedded system platform of heterogeneous multiprocessor. The heterogeneous multiprocessor platform is composed of an ARM7 general purpose processor and a DSP special purpose processor. The ARM processor handles the general operations of the platform while the DSP processor runs digital signal processing software and plays the role of programmable external device. Because the available memory space at DSP side is limited, the development of application program faces big challenge. This thesis takes the policy of trading time for space to design and implement the code overlay mechanism to address the issue of limited memory space.

The code overlay mechanism designed in this thesis has three characteristics: programmers don’t need to modify source code; without the restriction of compiler; there is just little overhead imposed on programmers and the mechanism is built on platform of heterogeneous multiprocessor. The implementation of the code overlay mechanism is composed of a preprocessing tool, dynamic code loading service on the ARM side and overlay manager on the DSP side. While the later two components implement the dynamic code overlay at run time, the preprocessing tool divides the application into segments, from the object program, in units of function modules to reduce the overhead incurred from loading overlays.

Code structure affects the effect of overlay mechanism in general. For application programs using the dynamic code overlay mechanism there is no need for programmers to modify source program structure because the target of preprocessing is object file and the performance impact is acceptable as observed from the result of testing. Therefore, the memory space used by application program can be reduced effectively.

[1] Analog Device, “Implementing Software Overlays on ADSP-218x DSPs with VisualDSP++”, 2004, Engineer To Engineer Note-249.
[2] Analog Device, “Using Memory Overlays”, 1999, Engineer To Engineer Note-66.
[3] Andrew S. Tanenbaum, Albert S. Woodhull, “Operating Systems – Design and Implementation”, Prentice Hall Inc., 1997, ISBN: 0-13-630195-9.
[4] Bernadine C. Lanazano, “Loader Standardization for Overlay Programs”, Communications of the ACM, Vol. 12, Number 9, October 1969.
[5] Bill Blunden, “Memory Management Algorithms and Implementation in C/C++”, Wordware Publishing Inc, 2003, ISBN: 1-55622-347-1.
[6] CDC, “Cyber Loader Version 1 Reference Manual”, Publication Number: 60429800, 1982.
[7] Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, and Sang Lyul Min, ”Compiler Assisted Demand Paging for Embedded Systems with Flash Memory”, The 4th ACM International Conference on Embedded Software (EMSoft 2004), Pisa, Italy, September, 2004.
[8] John R, “Linkers and Loaders”, Morgan Kaufmann, 2000, ISBN: 1-55-860496-0.
[9] Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha, “Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems”, Design, Automation and Test in Europe, 2006 (DATE '06), March, 2006.
[10] Texas Instruments, “TMS320C54x DSP Reference Set, Vol. 2: Mnemonic Instruction Set”, June, 1998.
[11] Texas Instruments, “TMS320DM270 CPU and Peripherals Technical Reference Manual Version 1.1”, September, 2003.
[12] Texas Instruments, “TMS470R1x Assembly Language Tools User’s Guide”, March, 1999.
[13] 徐偉智, 陳文欽, 游燦營, “嵌入式動態鏈結載入器設計及其在RSA演算法上的應用”, 中華民國第一屆應用科技研討會, 2004.
[14] 陳敬, 洪文斌, 歐旭江, “異質性多處理器嵌入式微核心系統之設計與實作”,
二○○五數位生活與網際網路科技研討會, 2005.
[15] 歐旭江, “異質性多處理器環境中資料流架構系統核心之設計與實作”, 碩士論文, 國立成功大學, June, 2005.