射頻收發器前端電路中，最重要的兩個電路為功率放大器與低雜訊放大器；功率放大器為發射器之最後一級，用以提高輸出功率，使訊號能夠完整傳輸至所需距離。低雜訊放大器為接收機之第一級，用以接收訊號，加以放大，並減少雜訊值，增加訊號傳輸的正確性。
在本篇論文中，學生將提出數個射頻放大器之設計，包含以下電路：3.1 ~ 4.8 GHz UWB超寬頻低雜訊放大器 (疊接式與折疊式兩種架構)、2.4GHz自我偏壓架構之線性化功率放大器、2.4/5.2 GHz 同步式雙頻功率放大器、3.1 ~ 4.8 GHz UWB超寬頻功率放大器。
超寬頻低雜訊放大器利用兩種不同架構，進行寬頻電路之設計：疊接式架構利用級間匹配電感，提高兩級間之匹配特性；折疊式架構利用NMOS與PMOS之折疊，提高增益並減少雜訊。
2.4GHz 線性化功率放大器是利用自我偏壓的架構，解決電路輸出失真問題，以提高P1dB與PAE，以達到線性化之功能。

2.4 / 5.2 GHz 雙頻功率放大器，應用電感與電容共振匹配電路，在輸入端與輸出端達到雙頻匹配，並提高其功率增益與輸出功率。
超寬頻功率放大器為兩級之放大器架構，以提高其功率增益，使輸出功率符合系統需求；輸入端匹配是以並聯-並聯回授架構形成，輸出端匹配以三級階梯式電感電容，同時達到寬頻輸出反射係數與功率匹配。在電路佈局方面，考量走線所造成之影響，學生利用電磁分析方法，將走線之寄生量進行粹取，獲取其S參數，並重新代入電路中，進行匹配電路之微調，以達到更準確的電路設計。

本論文中之電路設計是以TSMC 0.18um CMOS製程與UMC 0.18um CMOS製程之model進行模擬，並透過CIC之申請下線，完成晶片之製作。

Power amplifier and low noise amplifier are the most important blocks in the transceiver front-end. Power amplifier is the last stage of the transmitter. It amplifies the input signal to an enough output power level for transmitting through a long distance. Low noise amplifier is the first stage of the receiver. It can amplify the received signal and reduce the noise of the whole system in order to improve the accuracy of transmission.

In this work, we designed some radio frequency amplifiers, which contain 3.1~4.8 GHz Ultra-Wide band low noise amplifiers ( designed in cascode configuration with inter-stage matching and in folded-cascode configuration ), 2.4 GHz Self-biased cascode linearized power amplifier, 2.4/5.2 GHz concurrent dual-band power amplifier, and 3.1~4.8 GHz Ultra-Wide band power amplifier.

The ultra-wide band low noise amplifiers use two configurations to design the circuit. One is the cascode configuration with inter-stage matching inductor, the other is folded-cascode configuration. Both of these two configuration can improve the gain and lower the noise.

2.4GHz linearized power amplifier using the self-biased configuration to improve the linearity, the 1dB-compression point and power-added efficiency.
The 2.4/5.2 GHz concurrent dual-band power amplifier using LC resonating networks at the input and output to simultaneously arrive at the matching of reflection coefficient and output power.
The two-stage cascaded ultra-wide band power amplifier operating in the 3.1~4.8 GHz frequency range is presented. The shunt-shunt feedback is used to arrive at wideband matching. A ladder output network is exploited to achieve output match in wideband and to optimize the power performance. With EM simulation, the influence of lines in the layout can be considerated.

The circuits are implemented by TSMC 0.18um CMOS and UMC 0.18um CMOS process. These chips have also been fabricated by the support of CIC in Taiwan.

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