| 研究生: |
王玉琳 Wang, Yu-Lin |
|---|---|
| 論文名稱: |
建構於元件式電子系統層級的漸進式SOC設計流程 Incremental SOC Development Using Component-Based ESL Design-Ware |
| 指導教授: |
蘇文鈺
Su, Wen-Yu |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 73 |
| 中文關鍵詞: | 系統晶片設計 、事務級建模 、電子系統層級 |
| 外文關鍵詞: | Electronic System Level, SystemC, Transaction Level Modeling, SoC Design |
| 相關次數: | 點閱:141 下載:1 |
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隨著積體電路的迅速發展,所設計的硬體電路日益複雜,複雜度不斷增加,我們很難再依照過去傳統的設計方式,此時我們需要有新的一套設計流程來順應這種大型電路的設計。最近這幾年,電子系統層級設計的概念開始受到重視。ESL以抽象方式來描述一般晶片或甚至系統單晶片的設計,且速度快讓設計者有充裕的時間對設計內容進行詳細的分析,功能的細膩度足以提供虛擬原型,以配合軟體建置與展現硬體設計的程序可以使設計流程更順暢與模擬上更完整。因此ESL逐漸成為設計流程的基礎步驟,因為它不僅能應用在設計初期與系統架構規劃階段,亦能支援整個硬體與軟體互動設計的流程。
雖然有許多ESL的技術開始著墨於此一型態的開發作業,但是缺乏足夠的自動化輔助系統來強調子模組間處理資料的交換與在不同設計工具上開發的子模組共同驗證的議題。所以設計者還是必須在此些議題上花費相當多時間與精神,為解決上述之缺點,本論文提供一套設計驗證流程及工具,來處理子模組資料交換與系統溝通的工具並且讓在不同設計工具上開發的子模組可以進行共同模擬與驗證,並且可以利用多部電腦或多種不同的模擬工具的機制進行的漸進式模擬以加快設計流程。如此可讓設計者能更集中資源,專注在設計自己的子模組上,讓電路設計變的更簡單,更有效率,更低成本。
The complexity of hardware development becomes extremely high due to the rapid progress of VLSI design tools and the demanding of highly complex systems. New design flows are needed for designers to keep up with the new trend, since it’s difficult to carry out huge designs with traditional skills. In recent years, electronic system level (ESL) design has become one of the hottest topics. ESL describes a System-on-chip (SOC) design in the more abstract way and this makes faster system simulation while providing virtual prototypes (or models) for hardware and software co-design/co-verification. It is becoming a fundamental part of overall design flow. Furthermore, incremental (or iterative) design process can be applied to cover different design levels in the same design phase, rather than just in the architecture level and/or algorithm level.
There are many issues focusing on ESL development. In this thesis, we focus on the communication problems in the so-called Transactional Level Modeling (TLM) area. In the past, designers need to take care of both computation units and communication units at the same time. Here, we develop some useful development and interface tools so that the communication problems among computation models are reduced. We provide a centralized system development platform to manage the transaction in TLM. This platform allows designers to use tools such as FPGA, Matlab and Realview SOC Designers to perform simulation of the system if some models are available in other tools only. Furthermore, one can use multiple computers, each running certain number of models, to work together across internet for remote co-simulation. Hence, engineers could focus on their own modules to make the implementation easier, faster, and more reliable. Finally, we suggest that a new design flow which includes models implemented in different abstraction level to be considered together at the same time to make the design process easier.
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[2] 電子工程專輯 http://www.wwttaiwan.com/
[3] Brian Bailey, Grant Martin and Andrew Piziali, “ESL Design and Verification: A Prescription for Electronic System Level Methodology”, Morgan Kaufmann, 2007, ISBN: 0123735513
[4] SystemC http://www.systemc.org/
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[7] Lukai Cai and Daniel Gajsk, ”Transaction Level Modeling in System Level Design” CECS Technical Report, 2003.
[8] Co-Ware http://www.coware.com/
[9] Using System level modeling to enhance Soc verification lead-time
http://www.synopsys.com/products/cocentric_studio/francard_final.pdf
[10] AMBA protocol http://www.arm.com/products/solutions/AMBAHomePage.html
[11] Zhong, L.; Ravi, S.; Raghunathan, A.; Jha, N.K, “RTL-Aware Cycle-Accurate Functional Power Estimation”, computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions., Vol: 25, Issue 10, pp: 2103- 2117, Oct. 2006.
[12] 北瀚科技公司 http://www.smims.com/
[13] RealView SoC Designer http://www.arm.com/products/DevTools/MaxSim.html
[14] The Mathworks http://www.mathworks.com/
[15] Intel 8051 www.intel.com/design/mcs51/
[16] Kenneth J. Ayala “The 8051 Microcontroller – Architecture, Programming & Applications” 2nd edition, WEST, 1996. ISBN: 0314201882
[17] Altera DMA with Avalon interface http://www.altera.com/literature/hb/nios2/n2cpu_nii51006.pdf