由於草稿式記憶體 (Scratchpad Memory) 比常用的快取記憶體(Cache)有更小的能源消耗及面積，因此草稿式記憶體已經漸漸地被嵌入式系統使用。在快取記憶體和草稿式記憶體被提出之後，混合式晶片內建記憶體也被提出，混合式晶片內建記憶體含有一塊草稿式記憶體及一塊迷你快取記憶體。為了在混合式晶片內建記憶體架構下減少晶片外記憶體的存取次數，有些相關的研究將最常被存取的資料放到草稿式記憶體來。然而，這些方法可能是無效的，因為最常被存取的資料不一定是最常造成晶片外記憶體存取的資料。晶片外記憶體存取是快取記憶體失效造成的，所以減少快取記憶體失效次數才能減少晶片外記憶體存取次數。因此我們用快取記憶體失效次數來決定資料是否該搬到草稿式記憶體。我們提出了頁失效紀錄電路 (page miss bookkeeping circuit) 來統計每一頁資料的失效次數。當一頁資料的失效次數超過設定的門檻值就會被搬到草稿式記憶體。跟快取記憶體相比，我們的方法減少平均耗能延遲乘積 (EDP) 49%。跟在[19]所提出的方法相比，我們減少了平均耗能延遲乘積26%。

Scratchpad memories (SPM) have been increasingly used in embedded system due to their higher energy and area efficiency compared to ordinary caches. Hybrid on-chip memory architecture that combines SPM with a mini cache is also proposed. In order to reduce off-chip memory access in hybrid on-chip memory architecture, some related works put the most frequently accessed data into SPM. However, these methods may be ineffective because the most frequently accessed data may be not the main cause of off-chip memory access. Instead, off-chip memory accesses are caused by cache miss, and reducing cache misses can reduce off-chip memory accesses. Therefore, in this work, we propose using cache miss as a criterion to determine whether a page should be moved to SPM. We propose a page miss bookkeeping circuit to calculate the number of cache misses happened in a page. When the number of misses in a page is higher than a threshold, the page is moved to SPM. Compared to cache on-chip memory architecture, experimental results show our method can reduce the energy delay production (EDP) by 49%. Compare to the work in [19], our method can reduce the EDP by 26%.

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