隨著半導體產業的發展與推進，電晶體尺寸日新月異，每年不斷追尋著更優越的PPA (power、performance、area)。而如今，半導體技術節點已經逼近物理極限，若需繼續延續摩爾定律，不外乎由電晶體材料或電晶體結構等等來下手，以新材料、新結構創造出更高效能與更低功耗的電晶體元件。
本論文採用高遷移率通道材料-鍺作為元件通道材料，相對於傳統矽而言，鍺電子遷移率為其兩倍，且電洞遷移率高達四倍之多。然而¬¬，鍺之介面品質卻為製程上一大考驗，鍺氧化層容易因高溫產生揮發與水解情況，擴散至閘極介電層，導致漏電流上升，降低電晶體效能。故本論文利用氨電漿製作氮基底的介面層，此介面層具有較卓越的熱穩定性並提升介電層品質，並搭配三種不同常見高介電層材料，氧化鋁、二氧化鉿與二氧化锆，再搭配退火提升介面品質，追求最佳等效氧化層厚度與最佳電性。最後，作者利用氮化鉿介面層搭配出二氧化锆介電層，製作出等效氧化層厚度僅9埃的金氧半電容器。
最後，將上述金氧半電容器最佳參數條件，應用於鍺基板鰭式場效電晶體上。N型與P型鰭式場效電晶體開關特性皆達到近五個數量級，且次臨界擺幅皆約為100mv/dec。接著於N型與P型鰭式場效電晶體上利用金屬連線，完成反向器電路，並於其VTC轉換曲線，得到電壓增益約為20V/V，驗證了此鍺基板鰭式場效電晶體，可在實際電路運用的可能性。

With the development and advancement of the semiconductor industry, the size of transistors is changing with each passing day, and a better PPA (power, performance, area) is constantly being pursued every year. Today, the semiconductor technology node has approached the physical limit. If we need to continue Moore's Law, we must start with transistor materials or transistor structures, etc., and create higher performance and lower power consumption with new materials and new structures transistor components.
In this paper, germanium, a high-mobility channel material, is used as the device channel material. Compared with traditional silicon, germanium has twice the electron mobility and four times the hole mobility. However, the interface quality of germanium is a major challenge in the process. The germanium oxide layer is prone to volatilization and hydrolysis due to high temperature, and diffuses into the gate dielectric layer, resulting in an increase in leakage current and a decrease in transistor performance. Therefore, this paper uses ammonia plasma to fabricate a nitrogen-based interfacial layer. This interfacial layer has excellent thermal stability and improves the quality of the dielectric layer. Three different common high dielectric layer materials are used, aluminum oxide, hafnium dioxide, and zirconium dioxide, and then annealing to improve the interface quality, find the best equivalent oxide thickness, and improve the transistor performance. Finally, the author uses the hafnium nitride interfacial layer and zirconium oxide dielectric layer to fabricate a MOS capacitor with an equivalent oxide thickness of 9 angstroms.
Finally, the optimal parameter conditions of the MOS capacitor are applied to the germanium substrate fin field-effect transistor. Both n-type and p-type FinFETs Ion/Ioff reach nearly five orders of magnitude, and the subthreshold swing are both about 100mv/dec. Next, use metallization process on the n-type and p-type FinFETs to complete the inverter circuit, and the voltage transfer characteristic (VTC) with the maximum voltage gain of 20 V/V was achieved. This verifies the feasibility of the Ge fin field-effect transistors that can practically apply in circuits.

[1] C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "Germanium MOS capacitors incorporating ultrathin high-kappa gate dielectric," (in English), IEEE Electron Device Lett., Article vol. 23, no. 8, pp. 473-475, Aug 2002, doi: 10.1009/led.2002.801319.
[2] M. T. Bohr and I. A. Young, "CMOS scaling trends and beyond," IEEE Micro, vol. 37, no. 6, pp. 20-29, 2017.
[3] F. D’Agostino and D. Quercia, "Short-channel effects in MOSFETs," Introduction to VLSI design (EECS 467), vol. 70, pp. 71-72, 2000.
[4] J. Kavalieros et al., "Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering," in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006: IEEE, pp. 50-51.
[5] M. S. Lundstrom, "On the mobility versus drain current relation for a nanoscale MOSFET," IEEE Electron Device Lett., vol. 22, no. 6, pp. 293-295, 2001.
[6] K. J. Yang and C. Hu, "MOS capacitance measurements for high-leakage thin dielectrics," IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1500-1501, 1999.
[7] M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, "The high-k solution," IEEE spectrum, vol. 44, no. 10, pp. 29-35, 2007.
[8] R. D. Clark, "Emerging applications for high K materials in VLSI technology," Materials, vol. 7, no. 4, pp. 2913-2944, 2014.
[9] M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, "Fringing-induced drain current improvement in the tunnel field-effect transistor with high-$kappa $ gate dielectrics," IEEE transactions on electron devices, vol. 56, no. 1, pp. 100-108, 2008.
[10] A. Toriumi and T. Nishimura, "Germanium CMOS potential from material and process perspectives: Be more positive about germanium," Japanese Journal of Applied Physics, vol. 57, no. 1, p. 010101, 2017.
[11] F. Li, X. Liu, Y. Wang, and Y. Li, "Germanium monosulfide monolayer: a novel two-dimensional semiconductor with a high carrier mobility," Journal of Materials Chemistry C, vol. 4, no. 11, pp. 2155-2159, 2016.
[12] P. Yan, N. N. Lichtin, and D. L. Morel, "Amorphous silicon, germanium, and silicon‐germanium alloy thin‐film transistor performance and evaluation," Applied physics letters, vol. 50, no. 19, pp. 1367-1369, 1987.
[13] J. P. Colinge, "Multi-gate soi mosfets," Microelectronic Engineering, vol. 84, no. 9-10, pp. 2071-2076, 2007.
[14] M. L. A. E. SPERLING. "The Increasingly Uneven Race To 3nm/2nm." https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ (accessed.
[15] S. K. Wang et al., "Desorption kinetics of GeO from GeO 2/Ge structure," Journal of applied physics, vol. 108, no. 5, p. 054104, 2010.
[16] W.-H. Chang, H. Ota, and T. Maeda, "Gate-first high-performance germanium nMOSFET and pMOSFET using low thermal budget ion implantation after germanidation technique," IEEE Electron Device Lett., vol. 37, no. 3, pp. 253-256, 2016.
[17] C.-I. Wang et al., "Suppression of GeO x interfacial layer and enhancement of the electrical performance of the high-K gate stack by the atomic-layer-deposited AlN buffer layer on Ge metal-oxide-semiconductor devices," RSC advances, vol. 9, no. 2, pp. 592-598, 2019.
[18] J. Lin et al., "An investigation of capacitance-voltage hysteresis in metal/high-k/In0. 53Ga0. 47As metal-oxide-semiconductor capacitors," Journal of Applied Physics, vol. 114, no. 14, p. 144105, 2013.
[19] R. Winter, J. Ahn, P. C. McIntyre, and M. Eizenberg, "New method for determining flat-band voltage in high mobility semiconductors," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 31, no. 3, p. 030604, 2013.
[20] X.-F. Li, Y.-Q. Cao, A.-D. Li, H. Li, and D. Wu, "HfO2/Al2O3/Ge gate stacks with small capacitance equivalent thickness and low interface state density," ECS Solid State Letters, vol. 1, no. 2, p. N10, 2012.
[21] L. Zhang, H. Jiang, C. Liu, J. Dong, and P. Chow, "Annealing of Al2O3 thin films prepared by atomic layer deposition," Journal of Physics D: Applied Physics, vol. 40, no. 12, p. 3707, 2007.
[22] K. Yamamoto et al., "Electrical and structural properties of group-4 transition-metal nitride (TiN, ZrN, and HfN) contacts on Ge," Journal of Applied Physics, vol. 118, no. 11, p. 115701, 2015.
[23] S. Tan, "Control of interface traps in HfO2 gate dielectric on silicon," Journal of electronic materials, vol. 39, no. 11, pp. 2435-2440, 2010.