元件通道長度之縮短與閘極絕緣層厚度之降低，可有效提高元件積集密度，進而控制及降低半導體製程生產成本，並達到整合電路之功能性強化與效能提昇。然而，隨著閘極氧化層厚度之降低，元件可耐受之閘極電壓亦隨之降低。因此閘極氧化層可靠度驗證變成非常重要。
本論文中，吾人首先簡介了常見之可靠度驗證所利用之統計概念與工具，閘極氧化層之崩潰現象及常見於閘極氧化層可靠度驗證之 VRDB 及 SILC 量測方式。然後利用廣泛應用於靜電防護電路驗證之 TLP 技術來預先施予超薄閘極氧化層一高電壓脈衝，再透過 VRDB 之測試方法，評估超薄閘極氧化層之可靠度風險及其可耐受之最大閘極靜電電壓。此外，並找出最大脈衝電壓和閘極氧化層之崩潰電壓間關係，使 TLP 技術得以做為評估薄閘極氧化層之可靠度風險及其可耐受之最大閘極靜電電壓的一種簡便且不破壞之方法。

As the CMOS technology scales down to ultra deep sub-micron regime, the gate dielectric becomes very thin (≦1.45nm), thus the robustness of the thin gate dielectric for core devices is much more important. It is necessary to evaluate the reliability risk to further reconfirm the gate oxide integrity.

In this thesis, we develop a technique to evaluate the reliability of the gate oxide integrity. Firstly, a transmission line pulse (TLP) is applied on the thin gate dielectric to simulate the ESD (Electrostatic Discharge). And then, the common method VRDB (Voltage Ramp Dielectric Breakdown) is further taken for gate-oxide integrity verification. Meanwhile, the maximum tolerable pre-stress on such very thin gate dielectric is further confirmed.

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